SAM4L_14 Datasheet, PDF (77/176 Pages) ATMEL Corporation – Technology for Ultra-low Power Consumption

ATSAM4L8/L4/L2
8.8 AHB-AP Access Port
The AHB-AP is a Memory Access Port (MEM-AP) as defined in the ARM Debug Interface v5
Architecture Specification. The AHB-AP provides access to all memory and registers in the sys-
tem, including processor registers through the System Control Space (SCS). System access is
independent of the processor status. Either SW-DP or SWJ-DP is used to access the AHB-AP.
The AHB-AP is a master into the Bus Matrix. Transactions are made using the AHB-AP pro-
grammers model (please refer to the ARM Cortex-M4 Technical Reference Manual), which
generates AHB-Lite transactions into the Bus Matrix. The AHB-AP does not perform back-to-
back transactions on the bus, so all transactions are non-sequential. The AHB-AP can perform
unaligned and bit-band transactions. The Bus Matrix handles these. The AHB-AP transactions
are not subject to MPU lookups. AHB-AP transactions bypass the FPB, and so the FPB cannot
remap AHB-AP transactions. AHB-AP transactions are little-endian.
Note that while an external reset is applied, AHB-AP accesses are not possible. In addition,
access is denied when the protected state is set. In order to discard the protected state, a chip
erase operation is necessary.
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42023GS–SAM–03/2014