SAM4L_14 Datasheet, PDF (73/176 Pages) ATMEL Corporation – Technology for Ultra-low Power Consumption

ATSAM4L8/L4/L2
8.7.13
Security Restrictions
The SAM4L provide a security restrictions mechanism to lock access to the device. The device
in the protected state when the Flash Security Bit is set. Refer to section Flash Controller for
more details.
When the device is in the protected state the AHB-AP is locked. Full access to the AHB-AP is re-
enabled when the protected state is released by issuing a Chip Erase command. Note that the
protected state will read as programmed only after the system has been reseted.
8.7.13.1
Notation
Table 8-4 on page 73 shows bit patterns to be shifted in a format like "p01". Each character cor-
responds to one bit, and eight bits are grouped together for readability. The least significant bit is
always shifted first, and the most significant bit shifted last. The symbols used are shown in
Table 8-3.
Table 8-3. Symbol Description
Symbol Description
0
Constant low value - always reads as zero.
1
Constant high value - always reads as one.
p
The chip protected state.
x
A don’t care bit. Any value can be shifted in, and output data should be ignored.
e
An error bit. Read as one if an error occurred, or zero if not.
b
A busy bit. Read as one if the SMAP was busy, or zero if it was not.
s
Startup done bit. Read as one if the system has started-up correctly.
In many cases, it is not required to shift all bits through the data register. Bit patterns are shown
using the full width of the shift register, but the suggested or required bits are emphasized using
bold text. I.e. given the pattern "01010101 xxxxxxxx xxxxxxxx xxxxxxxx", the shift register is 32
bits, but the test or debug unit may choose to shift only 8 bits "01010101".
The following describes how to interpret the fields in the instruction description tables:
Table 8-4. Instruction Description
Instruction
Description
IR input value
Shows the bit pattern to shift into IR in the Shift-IR state in order to select this
instruction. The pattern is show both in binary and in hexadecimal form for
convenience.
Example: 1000 (0x8)
IR output value
Shows the bit pattern shifted out of IR in the Shift-IR state when this instruction is
active.
Example: p00s
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42023GS–SAM–03/2014