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| SAM4L_14 Datasheet, PDF (146/176 Pages) ATMEL Corporation – Technology for Ultra-low Power Consumption | |||
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ATSAM4L8/L4/L2
9.10.3 SPI Timing
9.10.3.1 Master mode
Figure 9-12. SPI Master Mode with (CPOL= NCPHA= 0) or (CPOL= NCPHA= 1)
SPCK
MISO
SPI0
SPI1
MOSI
SPI2
Figure 9-13. SPI Master Mode with (CPOL= 0 and NCPHA= 1) or (CPOL= 1 and NCPHA= 0)
SPCK
MISO
SPI3
SPI4
MOSI
SPI5
Table 9-62. SPI Timing, Master Mode(1)
Symbol
Parameter
Conditions
Min
Max
SPI0
MISO setup time before SPCK rises
9
SPI1
MISO hold time after SPCK rises
VVDDIO from
0
2.85V to 3.6V,
SPI2
SPCK rising to MOSI delay
maximum
9
21
SPI3
SPI4
MISO setup time before SPCK falls
MISO hold time after SPCK falls
external
7.3
capacitor =
40 pF
0
SPI5
SPCK falling to MOSI delay
9
22
Note: 1. These values are based on simulation. These values are not covered by test limits in production.
Maximum SPI Frequency, Master Output
Units
ns
42023GSâSAMâ03/2014
146
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