SAM4L_14 Datasheet, PDF (148/176 Pages) ATMEL Corporation – Technology for Ultra-low Power Consumption

ATSAM4L8/L4/L2
Figure 9-16. SPI Slave Mode, NPCS Timing
SPCK, CPOL=0
SPCK, CPOL=1
NPCS
SPI12
SPI14
SPI13
SPI15
Table 9-63. SPI Timing, Slave Mode⁽¹⁾
Symbol
Parameter
Conditions
Min
Max
SPI6
SPCK falling to MISO delay
19
47
SPI7
MOSI setup time before SPCK rises
0
SPI8
MOSI hold time after SPCK rises
5.4
SPI9
SPCK rising to MISO delay
V_VDDIO from
19
46
2.85V to 3.6V,
SPI10
MOSI setup time before SPCK falls
maximum
0
SPI11
MOSI hold time after SPCK falls
external
5.3
capacitor =
SPI12
NPCS setup time before SPCK rises
40 pF
4
SPI13
NPCS hold time after SPCK falls
2.5
SPI14
NPCS setup time before SPCK falls
6
SPI15
NPCS hold time after SPCK rises
1.1
Note: 1. These values are based on simulation. These values are not covered by test limits in production.
Units
ns
Maximum SPI Frequency, Slave Input Mode
The maximum SPI slave input frequency is given by the following formula:
f_SPCKMAX = MIN(f_CLKSPI,_S----_P-¹---_I--_n--)
Where SPIn is the MOSI setup and hold time, SPI7 + SPI8 or SPI10 + SPI11 depending on
CPOL and NCPHA. f_CLKSPI is the maximum frequency of the CLK_SPI. Refer to the SPI chap-
ter for a description of this clock.
Maximum SPI Frequency, Slave Output Mode
The maximum SPI slave output frequency is given by the following formula:
f_SPCKMAX = MIN(f_PINMAX,-_S---_P----_I--_n-----+--¹---_t-_S---_E----_T---_U---_P--)
42023GS–SAM–03/2014
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