SAM4L_14 Datasheet, PDF (124/176 Pages) ATMEL Corporation – Technology for Ultra-low Power Consumption

ATSAM4L8/L4/L2
9.7.3 Phase Locked Loop (PLL) Characteristics
Table 9-26. Phase Locked Loop Characteristics
Symbol
f_OUT
f_IN
I_PLL
Parameter
Output frequency ⁽¹⁾
Input frequency⁽¹⁾
Current consumption⁽¹⁾
Conditions
PLL is not availabe in PS1
fout=80MHz
fout=240MHz
Min
Typ
Max
48
240
4
16
200
500
Startup time, from enabling Wide Bandwidth mode disabled
8
t_STARTUP
the PLL until the PLL is
locked⁽¹⁾
Wide Bandwidth mode enabled
30
1.
These values are based on simulation. These values are not covered by test limits in production or characterization.
Unit
MHz
µA
µs
9.7.4 Digital Frequency Locked Loop (DFLL) Characteristics
Table 9-27.
Symbol
f_OUT
f_REF
I_DFLL
Digital Frequency Locked Loop Characteristics
Parameter
Output frequency ⁽¹⁾
Reference frequency⁽¹⁾
Accuracy⁽¹⁾
Conditions
DFLL is not availabe in PS1
FINE lock, f_REF = 32 kHz, SSG disabled ⁽²⁾
ACCURATE lock, f_REF = 32kHz, dither clk
RCSYS/2, SSG disabled⁽²⁾
FINE lock, f_REF = 8-150kHz, SSG
disabled⁽²⁾
ACCURATE lock, f_REF = 8-150kHz,
dither clk RCSYS/2, SSG disabled⁽²⁾
RANGE 0 96 to 220MHz
COARSE=0, FINE=0, DIV=0
RANGE 0 96 to 220MHz
COARSE=31, FINE=255, DIV=0
RANGE 1 50 to 110MHz
COARSE=0, FINE=0, DIV=0
Power consumption⁽¹⁾
RANGE 1 50 to 110MHz
COARSE=31, FINE=255, DIV=0
RANGE 2 25 to 55MHz
COARSE=0, FINE=0, DIV=1
RANGE 2 25 to 55MHz
COARSE=31, FINE=255, DIV=1
RANGE 3 20 to 30MHz
COARSE=0, FINE=0, DIV=1
RANGE 3 20 to 30MHz
COARSE=31, FINE=255, DIV=1
Min
20
8
430
1545
218
704
140
365
122
288
Typ
0.1
0.06
0.2
0.1
509
1858
271
827
187
441
174
354
Max
Unit
150
MHz
150
kHz
0.5
0.5
%
1
1
545
1919
308
862
µA
226
477
219
391
42023GS–SAM–03/2014
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