SAM4L_14 Datasheet, PDF (71/176 Pages) ATMEL Corporation – Technology for Ultra-low Power Consumption

ATSAM4L8/L4/L2
8.7.10
8.7.11
SW-DP and JTAG-DP Selection Mechanism
After reset, the SWJ-DP is in JTAG mode but it can be switched to the Serial Wire mode. Debug
port selection mechanism is done by sending specific SWDIOTMS sequence. The JTAG-DP is
selected by default after reset.
• Switch from JTAG-DP to SW-DP. The sequence is:
– Send more than 50 SWCLKTCK cycles with SWDIOTMS = 1
– Send the 16-bit sequence on SWDIOTMS = 0111100111100111 (0x79E7 MSB first)
– Send more than 50 SWCLKTCK cycles with SWDIOTMS = 1
• Switch from SWD to JTAG. The sequence is:
– Send more than 50 SWCLKTCK cycles with SWDIOTMS = 1
– Send the 16-bit sequence on SWDIOTMS = 0011110011100111 (0x3CE7 MSB
first)
Send more than 50 SWCLKTCK cycles with SWDIOTMS = 1
Note that the BSCAN-TAP is not available when the debug port is switched to Serial Mode.
Boundary scan instructions are not available.
JTAG-DP and BSCAN-TAP Selection Mechanism
After the DP has been enabled, the BSCAN-TAP and the JTAG-DP run simultaneously has long
as the SWJ-DP remains in JTAG mode. Each TAP captures simultaneously the JTAG instruc-
tions that are shifted. If an instruction is recognized by the BSCAN-TAP, then the BSCAN-TAP
TDO is selected instead of the SWJ-DP TDO. TDO selection changes dynamically depending on
the current instruction held in the BSCAN-TAP instruction register.
71
42023GS–SAM–03/2014