DS742 Datasheet, PDF (9/33 Pages) Xilinx, Inc – Programable clock phase and polarity

LogiCORE IP AXI Serial Peripheral Interface (AXI SPI) (v1.02.a)
SPI Status Register (SPISR)
The SPI Status Register (SPISR) is a read-only register that gives the programmer visibility of the status of some
aspects of the AXI SPI IP core. The bit assignment in the SPISR is shown in Figure 4 and described in Table 7.
Writing to the SPISR does not modify the register contents.
X-Ref Target - Figure 4
Reserved
Tx_Empty
MODF
Rx_Empty
31
65 4 321 0
Rx_Full
Slave_Mode Tx_Full
_Select
DS742_04
Figure 4: SPI Status Register (C_BASEADDR + 0x64)
Table 7: SPI Status Register (SPISR) Description (C_BASEADDR + 0x64)
Bit(s)
Name
Core Reset
Access Value
Description
31 - 6 Reserved N/A N/A Reserved
Slave_Mode_Select Flag
Slave_
This flag is asserted when the core is configured in slave mode. Slave_Mode_Select is
5
Mode_ Read
1 activated as soon as the master SPI core asserts the Chip Select pin for the core.
Select
1 = Default
0 = Asserted when core configured in slave mode and selected by external SPI master
Mode-Fault Error Flag (Mode-fault Error)
This flag is set if the SS signal goes active while the SPI device is configured as a
4
MODF Read
0 ^{master. MODF is automatically cleared by reading the SPISR. A low-to-high MODF}
transition generates a single-cycle strobe interrupt.
0 = No error
1 = Error condition detected
Transmit Full
When a transmit FIFO exists, this bit is set high when the transmit FIFO is full.
3 Tx_Full Read 0
Note: When FIFOs do not exist, this bit is set high when an AXI write to the transmit
register has been made. This bit is cleared when the SPI transfer is completed.
2 Tx_Empty Read
Transmit Empty
When a transmit FIFO exists, this bit is set high when the transmit FIFO is empty. The
occupancy of the FIFO is decremented with the completion of each SPI transfer.
1
Note: When FIFOs do not exist, this bit is set with the completion of an SPI transfer.
Either with or without FIFOs, this bit is cleared upon a AXI write to the FIFO or transmit
register.
Receive Full
When a receive FIFO exists, this bit is set high when the receive FIFO is full. The
1
Rx_Full Read
0 ^{occupancy of the FIFO is incremented with the completion of each SPI transaction.}
Note: When FIFOs do not exist, this bit is set high when an SPI transfer has
completed. Rx_Empty and Rx_Full are complements in this case.
0 Rx_Empty Read
Receive Empty
When a receive FIFO exists, this bit is set high when the receive FIFO is empty. The
1 ^{occupancy of the FIFO is decremented with each FIFO read operation.}
Note: When FIFOs do not exist, this bit is set high when the receive register has been
read. This bit is cleared at the end of a successful SPI transfer.
DS742 January 18, 2012
www.xilinx.com
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Product Specification