DS742 Datasheet, PDF (31/33 Pages) Xilinx, Inc – Programable clock phase and polarity

LogiCORE IP AXI Serial Peripheral Interface (AXI SPI) (v1.02.a)
List of Acronyms
Acronym
AMBA
ARM
AXI
BRG
CPHA
CPOL
DDR
DGIER
DRR
DTR
DUT
EDK
EEPROM
FF
FIFO
FPGA
GPIO
I/O
IP
IPIC
IPIER
IPIF
IPISR
ISE
LSB
LUT
MISO
MODF
MOSI
MSB
RAM
Rx
SCK
SPI
SPICR
SPIDRR
SPIDTR
SPIE
Description
Advanced Microcontroller Bus Architecture
Advanced RISC Machine
Advanced eXtensible Interface
Baud Rate Generator
Clock Phase
Clock Polarity
Double Data Rate
Device Global Interrupt Enable Register
Data Receive Register
Data Transmit Register
Device Under Test
Embedded Development Kit
Electrically Erasable Programmable Read-Only Memory
Flip-Flop
First In First Out
Field Programmable Gate Array
General Purpose Input/Output
Input/Output
Intellectual Property
IP Interconnect
IP interrupt enable register
IP Interface
IP Interrupt Status Register
Integrated Software Environment
Least Significant Bit
Lookup Table
Master In Slave Out
Mode-fault Error
Master Out Slave In
Most Significant Bit
Random Access Memory
Receive
Serial Clock
Serial Peripheral Interface
SPI Control Register
SPI Data Receive Register
SPI Data Transmit Register
SPI Interrupt Enable
DS742 January 18, 2012
www.xilinx.com
31
Product Specification