DS742 Datasheet, PDF (25/33 Pages) Xilinx, Inc – Programable clock phase and polarity

LogiCORE IP AXI Serial Peripheral Interface (AXI SPI) (v1.02.a)
11. Read IPISR of both master and slave SPI devices as required.
12. Perform interrupt requests as required.
13. Read SPISR of both master and slave SPI devices as required.
14. Perform actions as required or dictated by SPISR data.
Steps to be followed when the core is configured in slave mode
1. Set the desired clock ratio using C_SCK_RATIO = up to 4 is allowed.
2. Fill the SPIDTR with the data; enable the interrupts as required for slave mode.
3. Enable the slave mode through SPICR and enable the core through SPE.
4. Connect the SPISEL input of the core to the Chip Select signal of external master SPI core.
5. Select the core using the active Low SPISEL bit .
6. After the core is selected by asserting the SPISEL, the core waits for the master’s clock on SCK line and inputs
on the MOSI line.
7. When the master starts the clock, data is exchanged between the master and slave on MISO and MOSI line
respectively.
8. After each exchange of 8 bit of data, the core performs local housekeeping work. This includes storing the
received data in the SPIDRR, loading the new data from SPIDTR into the local shift register for a new transfer
and resetting the internal counter for the next transfer.
9. All the internal processes in step 8 take approximately 4 AXI clock cycles. It is preferable to allow an idle time
of 6 clocks in between 2 consecutive transactions.
10. The core transfers the data until its DRR FIFO is empty. When the complete transfer is finished from the core the
interrupt sets to indicate that the DRR is empty and the DTR is full. At this point, unless the DTR is re-filled, the
core cannot communicate with master.
11. Read the DRR and re-fill the DTR and repeat the steps above.
Design Constraints
Timing Constraints
When the core is added in the MHS of XPS build, the timing constraints for the core are taken care at the system
level by the XPS tool.
Design Implementation
Target Technology
The target FPGA technologies for the core are the supported device families listed in the LogiCORE IP Facts.
Device Utilization and Performance Benchmarks
Core Performance
Because the AXI SPI IP core is used with other design modules in the FPGA, the utilization and timing numbers
reported in this section are estimates only. When the core is combined with other designs in the system, the
utilization of FPGA resources and timing of the core design can vary from the results reported here.
The core resource utilization for various parameter combinations measured with a Artix™-7 FPGA as the target
device are detailed in Table 16.
DS742 January 18, 2012
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Product Specification