DS742 Datasheet, PDF (21/33 Pages) Xilinx, Inc – Programable clock phase and polarity

LogiCORE IP AXI Serial Peripheral Interface (AXI SPI) (v1.02.a)
When external slave SPI devices are implemented, SCK, MOSI and MISO, as well as the needed SS(N) signals, are
brought out to pins. All signals are true 3-state bus signals and erroneous external bus activity can corrupt internal
transfers when both internal and external devices are present.
The user must ensure that the external pull-up or pull-down of external SPI 3-state signals are consistent with the
sink/source capability of the FPGA I/O drivers. Recall that the I/O drivers can be configured for different drive
strengths as well as internal pull-ups. The 3-state signals for multiple external slaves can be implemented as per
system design requirements, but the external bus must follow the SPI M68HC11 specifications.
CPHA Equals One Transfer Format
With CPHA = 1, the first SCK cycle begins with an edge on the SCK line from its inactive level to active level (rising
or falling depending on CPOL) as shown in Figure 15. The waveforms are shown for CPOL = 0, LSB First = 0, and
the value of generic C_SCK_RATIO = 4. All AXI and SPI signals have the same relation with respect to SAXI_Clk
and SCK, respectively.
X-Ref Target - Figure 15
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Figure 15: Data Write-Read Cycle on SPI Bus with CPHA = 1 and SPICR(24) = 0 for 8-bit Data
SPI Protocol Slave Select Assertion Modes
The SPI protocol is designed to have automatic slaves select assertion and manual slave select assertion which are
described in the following sections. All the SPI transfer formats described in SPI Clock Phase and Polarity Control
section are valid for both Automatic and Manual slave select assertion mode.
SPI Protocol with Automatic Slave Select Assertion
This section describes the SPI protocol where slave select (SS(N)) is asserted automatically by the SPI master device
(SPICR bit(7) = 0). This is the configuration mode provided to allow transfer of data with automatic toggling of the
slave select (SS) signal until all the elements are transferred. In this mode the data in the SPISSR register appears on
the SS(N) output when the new transfer starts. After every byte (or element) transfer, the SS(N) output goes to 1.
The data in SPISSR register again appears on the SS(N) output at the beginning of a new transfer. The user does not
need to manually control the slave select signal.
SPI Protocol with Manual Slave Select Assertion
This section briefly describes the SPI protocol where the slave select (SS(N)) is manually asserted by the user (that
is, SPICR bit(7) = 1). This is the configuration mode provided to allow transfers of an arbitrary number of elements
without toggling the slave select until all the elements are transferred. In this mode, the data in the SPISSR register
appears directly on the SS(N) output. SCK must be stable before the assertion of slave select. Therefore, when
manual slave select mode is used, the SPI master must be enabled first (SPICR bit(7) = 1) to assert SCK to the idle
state prior to asserting slave select.
DS742 January 18, 2012
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Product Specification