DS742 Datasheet, PDF (23/33 Pages) Xilinx, Inc – Programable clock phase and polarity

LogiCORE IP AXI Serial Peripheral Interface (AXI SPI) (v1.02.a)
When the AXI SPI IP core is configured with FIFOs and a series of consecutive SPI 8-bit/16-bit/32-bit element
transfers are performed, SPISR bits and IPISR do indicate completion of the first and the last SPI transfers with no
indication of intermediate transfers. The only way to monitor when intermediate transfers are completed is to
monitor the receive FIFO occupancy number. There is also an interrupt when the transmit FIFO is half empty, bit(6)
of IPISR. When the SPI device is configured as a slave, the setting/clearing of the bits discussed previously for a
master coincides with the setting/clearing of the master bits for both cases of CPHA = 0 and CPHA = 1. Recall that
for CPHA = 1 (that is, no SCK edge denoting the end of the last clock period) the slave has no way of knowing when
the end of the last SCK period occurs unless an AXI clock period counter was included in the SPI slave device.
SPI Registers Flow Description
This section provides information on setting the SPI registers to initiate and complete bus transactions.
SPI master device with or without FIFOs where the slave select vector is asserted manually via SPICR
bit(24) assertion.
This flow allows the transfer of N number of byte/half-word/word by toggling of the slave select vector just once.
This is the default mode of operation. The user can follow the subsequent steps to successfully complete an SPI
transaction:
1. Start from proper state including SPI bus arbitration.
2. Configure Device Global Interrupt Enable Register (DGIER) and IPIER registers as desired.
3. Configure target slave SPI device as required. This includes configuration of the DTR and Control Register of
slave SPI core and enabling it.
4. Write initial data to master SPIDTR register/FIFO. This assumes that the SPI master is disabled.
5. Ensure the SPISSR register has all ones.
6. Write configuration data to master SPI device SPICR as desired including setting bit(7) for manual asserting of
SS vector and setting both enable bit and master transfer inhibit bit. This initializes SCK and MOSI but inhibits
transfer.
7. Write to SPISSR to manually assert SS vector.
8. Write the preceding configuration data to master SPI device SPICR, but clear inhibit bit which starts transfer.
9. Wait for interrupt (typically IPISR bit(4)) or poll status for completion. Wait time depends on SPI clock ratio.
10. Set master transaction inhibit bit to service interrupt request. Write new data to master register/FIFOs and
slave device and then clear master transaction inhibit bit to continue N 8-bit element transfer. An overrun of the
SPIDRR register/FIFO can occur if the SPIDRR register/FIFOs are not read properly. In addition, SCK will have
stretched idle levels between element transfers (or groups of element transfers if utilizing FIFOs) and MOSI can
transition at the end of a element transfer (or group of transfers), but will be stable at least one-half SCK period
prior to sampling edge of SCK.
11. Repeat previous two steps until all data is transferred.
12. Write all ones to SPISSR or exit manual slave select assert mode to deassert SS vector while SCK and MOSI are
in the idle state.
13. Disable devices as desired.
SPI master and slave devices without FIFOs performing one 8-bit/16-bit/32-bit transfer (optional mode)
Follow these steps to complete an SPI transaction:
1. Start from proper state including SPI bus arbitration.
2. Configure master DGIER and IPIER. Also configure slave DGIER and IPIER registers as desired.
DS742 January 18, 2012
www.xilinx.com
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Product Specification