DS742 Datasheet, PDF (30/33 Pages) Xilinx, Inc – Programable clock phase and polarity

LogiCORE IP AXI Serial Peripheral Interface (AXI SPI) (v1.02.a)
Specification Exceptions
Exceptions from the Motorola M68HC11-Rev. 4.0 Reference Manual
1. A slave mode-fault error interrupt is added to provide an interrupt if a SPI device is configured as a slave and
is selected when not enabled.
2. In this design, the SPIDTR and SPIDRR registers have independent addresses. This is an exception to the
M68HC11 specification which calls for two registers to have the same address.
3. All SS signals are required to be routed between SPI devices internally to the FPGA. This is because toggling of
the SS signal is utilized in slaves to minimize FPGA resources.
4. Manual control of the SS signals is provided by setting bit(7) in the SPICR register. When the device is
configured as a master and is enabled and bit(7) of the SPICR register is set, the vector in the SPISSR register is
asserted. When this mode is enabled, multiple elements can be transferred without toggling the SS vector.
5. A control bit is provided to inhibit master transfers. This bit is effective in any master mode, but its main utility
is for manual control of the SS signals.
6. In the M68HC11 implementation, the transmit register is transparent to the shift register which necessitates the
write collision error (WCOL) detection hardware. This is not implemented in this design.
7. The interrupt enable bit (SPIE) defined by the M68HC11 specifications which resides in the M68HC11 control
register has been moved to the IPIER register. In the position of the SPIE bit, there is a bit to select local master
loopback mode for testing.
8. An option is implemented in this FPGA design to implement FIFOs on both transmit and receive (Full Duplex
only) mode.
9. M68HC11 implementation supports only byte transfer. In this design either a byte, half-word or word transfer
can be configured via a generic C_NUM_TRANSFER_BITS.
10. The baud rate generator is specified by Motorola to be programmable via bits in the control register; however,
in this FPGA design the baud rate generator is programmable via parameters in the VHDL implementation.
Therefore, in this implementation, run time configuration of the baud rate is not possible. Furthermore, in
addition to the ratios of 2, 4, 16 and 32, all integer multiples of 16 up to 2048 are allowed.
11. The AXI SPI IP core is tested with Atmel AT45DB161D and ST Microelectronics M25P16 serial SPI slave devices.
These devices support SPI modes 0 and 3. These devices have data valid time of 8 ns from the falling edge of
SCK. While operating with these devices at higher speed of 50 MHz (most instructions supports this speed), the
core should be configured in C_SCK_RATIO = 2 mode (where the AXI is configured to operate at 100 MHz).
Due to limited time availability in the design as well as real SPI slave behavior for data change, the data in the
SPI core is registered in the middle of each falling edge and the next consecutive rising edge. As per the
M68HC11 document, the master should register data on each rising edge of SCK in SPI modes 1 and 3. Note
that the data registering mechanism when C_SCK_RATIO =2 follows a different pattern than specified in the
standard (this is applicable to the data registering mechanism in the IP core only). The SPI core when
configured in master mode changes data on each falling edge and this behavior is as per the M68HC11
standard.
12. When the AXI SPI IP core is configured in slave mode, the data in the core is registered on the SCK rising edge
+ 1 AXI clock signal. Internally, this data is registered on the next rising edge of AXI. The core changes the data
on the SCK falling edge + AXI clock cycle.
DS742 January 18, 2012
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Product Specification