DS742 Datasheet, PDF (18/33 Pages) Xilinx, Inc – Programable clock phase and polarity

LogiCORE IP AXI Serial Peripheral Interface (AXI SPI) (v1.02.a)
The transmit FIFO is write-only. When data is written in the FIFO, the occupancy number is incremented and when
an SPI transfer is completed, the number is decremented. As a consequence of this operation, aborted SPI transfers
still have the data available for the transmission retry. The transfers can only be aborted in the master mode by
setting Master Transaction Inhibit bit, bit(23) of SPICR to 1 during a transfer. Setting this bit in the slave mode has
no effect on the operation of the slave. These aborted transfers are on the SPI interface. The occupancy number is a
read-only register.
If a write is attempted when the FIFO is full, then an acknowledgement is given along with an error signal
generation. Interrupts associated with the transmit FIFO include data transmit FIFO empty, transmit FIFO half
empty and transmit FIFO underrun. See the section on Interrupt Register Set Description for details.
The receive FIFO is read-only. When data is read from the FIFO, the occupancy number is decremented and when
an SPI transfer is completed, the number is incremented. If a read is attempted when the FIFO is empty, then
acknowledgement is given along with an error signal generation. When the receive FIFO becomes full, the receive
FIFO full interrupt is generated. Data is automatically written to the FIFO from the SPI module shift register after
the completion of an SPI transfer. If the receive FIFO is full and more data is received, then a receive FIFO overflow
interrupt is issued. When this happens, all data attempted to be written to the full receive FIFO by the SPI module
is lost.
SPI transfers, when the AXI SPI IP core is configured with FIFOs, can be started in two different ways depending on
when the enable bit in the SPICR is set. If the enable bit is set prior to the first data being loaded in the FIFO, then
the SPI transfer begins immediately after the write to the master transmit FIFO. If the FIFO is emptied via SPI
transfers before additional elements are written to the transmit FIFO, an interrupt is asserted. When the AXI to SPI
SCK frequency ratio is sufficiently small, this scenario is highly probable. Alternatively, the FIFO can be loaded up
to 16 elements and then the enable bit can be set which starts the SPI transfer. In this case, an interrupt is issued after
all elements are transferred. In all cases, more data can be written to the transmit FIFOs to increase the number of
elements transferred before emptying the FIFOs.
Local Master Loopback Operation
Local master loopback operation, although not included in the M68HC11 reference manual, has been implemented
to expedite testing. This operation is selected via setting the loopback bit in the SPICR; the transmitter output is
internally connected to the receiver input. The receiver and transmitter operate normally, except that received data
(from a remote slave) is ignored. This operation is relevant only when the SPI device is configured as a master.
Hardware Error Detection
The SPI architecture relies on software controlled bus arbitration for multi-master configurations to avoid conflicts
and errors. However, limited error detection is implemented in the SPI hardware. The first error detection
mechanism to be discussed is contention error detection. This detects when an SPI device configured as a master is
selected (that is, its SS bit is asserted) by another SPI device simultaneously configured as master.
In this scenario, the master being selected as a slave immediately drives its outputs as necessary to avoid hardware
damage due to simultaneous drive contention. The master also sets the mode-fault error (MODF) bit in the SPISR.
This bit is automatically cleared by reading the SPISR. Following a MODF error, the master must be disabled and
re-enabled with correct data. When configured with FIFOs, this might require clearing the FIFOs.
A similar error detection mechanism has been implemented for SPI slave devices. The error detected is when a SPI
device configured as a slave but is not enabled and is selected (that is, its SS bit is asserted) by another SPI device.
When this condition is detected, IPISR bit(1) is set by a strobe to the IPISR register.
DS742 January 18, 2012
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Product Specification