DS742 Datasheet, PDF (33/33 Pages) Xilinx, Inc – Programable clock phase and polarity

LogiCORE IP AXI Serial Peripheral Interface (AXI SPI) (v1.02.a)
Revision History
Date
09/21/10
Version
1.0
09/21/10
09/28/10
12/14/10
1.0.1
1.1
1.2
6/22/11
1.3
7/6/11
1.3.1
10/19/11
1.4
01/18/12
1.5
Revision
First release of the core with AXI interface support. The previous release of this
document was ds570.
Documentation only. Added inferred parameters text on page 4.
Updated version and utilization table.
Updated to v1.01.a version; updated tools to 12.4.
Updated for 13.2 release; removed Design Constraints section; added 7 series
support; modified Timing Constraints section; modified Allowable value for
C_SCK_RATIO in Table 1.
Corrected verbiage for LogiCORE Facts table footnote 1.
Summary of Major Core Version Changes
• Updated to v1.02.a version
• Updated tools to 13.3
• Fixed CR610995 - SPI slave Select Endianness is corrected
Summary of Major Documentation Changes
• Updated Notice of Disclaimer
• Updated List of Acronyms
• In Core Performance section, listed the latest device to earliest device: Artix-7,
Virtex-7, Kintex-7, Virtex-6, and Spartan-6
• Added information about IPIC on page 3
• Corrected Figures 14 and 15
• Updated to newest FrameMaker template
Added Steps to be followed when the core is configured in slave mode, page 25.
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DS742 January 18, 2012
www.xilinx.com
33
Product Specification