DS742 Datasheet, PDF (28/33 Pages) Xilinx, Inc – Programable clock phase and polarity

LogiCORE IP AXI Serial Peripheral Interface (AXI SPI) (v1.02.a)
Table 20: Performance and Resource Utilization Benchmarks on a Spartan-6 FPGA (xc6slx45tfgg484-3)
Parameter Values
(other parameters at default values)
Device Resources
Performance
Slices
Slice Flip-
Flops
LUTs
Fmax (MHz)
0
2
2
1
2
2
0
4
2
1
4
2
0
32
2
1
32
2
8
85
138
155
125
8
96
138
206
128
8
109
153
192
133
8
105
150
230
127
8
92
155
182
135
8
109
154
235
130
System Performance
To measure the system performance (F_MAX) of this core, the core was added to a Virtex-6 FPGA system and a
Spartan-6 FPGA system as the device under test (DUT) as illustrated in Figure 16.
Because the AXI SPI core is used with other design modules in the FPGA, the utilization and timing numbers
reported in this section are estimates only. When this core is combined with other designs in the system, the design’s
FPGA resources and timing usage can vary from the results reported here.
The target FPGA was filled with logic to drive the LUT and block RAM utilization to approximately 60% and the
I/O utilization to approximately 80%. Using the default tool options and the slowest speed grade for the target
FPGA, the resulting target FMAX numbers are shown in Table 21.
DS742 January 18, 2012
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Product Specification