DS742 Datasheet, PDF (20/33 Pages) Xilinx, Inc – Programable clock phase and polarity

LogiCORE IP AXI Serial Peripheral Interface (AXI SPI) (v1.02.a)
the SS(N) line can remain active Low between successive transfers. The specification states that this format is useful
in systems with a single master and single slave. In the context of the M68HC11 specification, transmit data is
placed directly in the shift register upon a write to the transmit register. Consequently, it is the user’s responsibility
to ensure that the data is properly loaded in the SPISSR register prior to the first SCK edge.
The SS signal is toggled for all CPHA configurations and there is no support for SPISEL being held low. It is
required that all SS signals be routed between SPI devices internally to the FPGA. Toggling the SS signal reduces
FPGA resources. The different transfer formats are described in the following sections.
CPHA Equals Zero Transfer Format
Figure 14 shows the timing diagram for an SPI data write-read cycle when CPHA = 0. The waveforms are shown for
CPOL = 0, LSB First = 0, and the value of generic C_SCK_RATIO = 4. All AXI and SPI signals have the same relation
with respect to S_AXI_AClk and SCK, respectively.
X-Ref Target - Figure 14
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Figure 14: Data Write-Read Cycle on SPI Bus with CPHA = 0 and SPICR(24) = 0 for 8-bit Data
Signal SCK remains in the idle state until one-half period following the assertion of the slave select line which
denotes the start of a transaction. Because assertion of the SS(N) line denotes the start of a transfer, it must be
deasserted and re-asserted for sequential element transfers to the same slave device.
One bit of data is transferred per SCK clock period. Data is shifted on one edge of SCK and is sampled on the
opposite edge when the data is stable. Consistent with the M68HC11 SPI specification, selection of clock polarity
and a choice of two different clocking protocols on an 8-bit/16-bit/32-bit oriented data transfer is possible via bits
in the SPICR.
The MOSI and MISO ports behave differently depending on whether the SPI device is configured as a master or a
slave. When configured as a master, the MOSI port is a serial data output port and the MISO is a serial data input
port. The opposite is true when the device is configured as a slave; the MISO port is a slave serial data output port
and the MOSI is a serial data input port. There can be only one master and one slave transmitting data at any given
time. The bus architecture provides limited contention error detection (that is, multiple devices driving the shared
MISO and MOSI signals) and requires the software to provide arbitration to prevent possible contention errors.
All SCK, MOSI, and MISO pins of all devices are respectively hardwired together. For all transactions, a single SPI
device is configured as a master and all other SPI devices on the SPI bus are configured as slaves. The single master
drives the SCK and MOSI pins to the SCK and MOSI pins of the slaves. The uniquely selected slave device drives
data out from its MISO pin to the MISO master pin, thus realizing full-duplex communication. The Nth bit of the
SS(N) signal selects the Nth SPI slave with an active Low signal. All other slave devices ignore both SCK and MOSI
signals. In addition, the non-selected slaves (that is, SS pin high) drive their MISO pin to 3-state so as not to interfere
with SPI bus activities.
DS742 January 18, 2012
www.xilinx.com
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Product Specification