DS742 Datasheet, PDF (13/33 Pages) Xilinx, Inc – Programable clock phase and polarity

LogiCORE IP AXI Serial Peripheral Interface (AXI SPI) (v1.02.a)
IP Interrupt Status Register (IPISR)
Up to nine unique interrupt conditions are possible depending upon whether the system is configured with FIFOs
or not as well as if it is configured in master mode or slave mode. A system without FIFOs has seven interrupts. The
interrupt controller has the 32-bit Interrupt Status Register that can enable each interrupt independently. This
register collects all of the interrupt events. Bit assignments are shown in Figure 11 and described in Table 14. The
interrupt register is a read/toggle on write register. Writing a 1 to a bit position within the register causes the
corresponding bit to toggle. All register bits are cleared upon reset.
X-Ref Target - Figure 11
Reserved
DRR_Not_Empty
DRR
Full
Tx FIFO
DTR
Half Empty
Empty MODF
31
987654 3210
DRR
Slave
Over-run
MODF
Slave
DTR
Mode_Select ^Under-run
Figure 11: IP Interrupt Status Register (IPISR) (C_BASEADDR + 0x20)
DS742_11
Table 14: IP Interrupt Status Register (IPISR) Description (C_BASEADDR + 0x20)
Bit(s) Name
Access
Reset
Value
Description
31 - 9 Reserved
N/A
N/A Reserved
DRR Not Empty
IPISR bit(8) is the DRR Not Empty bit.
The assertion of this bit is applicable only in the case where C_FIFO_EXIST = 1 and
the core is configured in slave mode. This bit is set when the DRR FIFO receives the
8
DRR_Not_
Empty
R/TOW⁽¹⁾
0
first data value during the SPI transaction. This bit is set by one-clock period strobe
to the interrupt register when the core receives first data beat.
Note: The assertion of this bit is applicable only when the C_FIFO_EXIST = 1 and
the core is configured in slave mode. In C_FIFO_EXIST = 0, this bit always return 0.
It is recommended to use this bit only when C_FIFO_EXIST = 1 and the core is
configured in slave mode.
Slave Select Mode
IPISR bit(7) is the Slave Select Mode bit.
7
Slave_
Select_
Mode
R/TOW⁽¹⁾
0
The assertion of this bit is applicable only when the core is configured in slave mode.
This bit is set when the other SPI master core selects the core by asserting the Slave
Select line. This bit is set by one-clock period strobe to the interrupt register.
Note: This bit is applicable only when the core is configured in the slave mode.
Transmit FIFO Half Empty
IPISR bit(6) is the transmit FIFO half-empty interrupt. This bit is set by a one-clock
6
Tx FIFO
Half Empty
R/TOW⁽¹⁾
0
period strobe to the interrupt register when the occupancy value is decremented
from "1000" to "0111". The value "0111" means there are 8 elements in the FIFO
to be transmitted.
Note: This interrupt exists only if the AXI SPI IP core is configured with FIFOs.
Data Receive Register/FIFO Overrun
5
DRR
Overrun
R/TOW⁽¹⁾
0
IPISR bit(5) is the data receive FIFO overrun interrupt. This bit is set by a one-clock
period strobe to the interrupt register when an attempt to write data to a full receive
register or FIFO is made by the SPI core logic to complete an SPI transfer.
This can occur when the SPI device is in either master or slave mode.
DS742 January 18, 2012
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Product Specification