DS742 Datasheet, PDF (10/33 Pages) Xilinx, Inc – Programable clock phase and polarity

LogiCORE IP AXI Serial Peripheral Interface (AXI SPI) (v1.02.a)
SPI Data Transmit Register (SPIDTR)
This register is written to with the data to be transmitted on the SPI bus. After the SPE bit is set to 1 in master mode
or SPISEL is active in the slave mode, the data is transferred from the SPIDTR to the shift register. If a transfer is in
progress, the data in the SPIDTR is loaded in the shift register as soon as the data in the shift register is transferred
to the SPIDRR and a new transfer starts. The data is held in the SPIDTR until a subsequent write overwrites the
data. The SPIDTR is shown in Figure 5, while Table 8 shows specifics of the data format. When a transmit FIFO
exists, data is written directly in the FIFO and the first location in the FIFO is treated as the SPIDTR. The pointer is
decremented after completion of each SPI transfer.
This register cannot be read and can only be written when it is known that space for the data is available. If an
attempt to write is made on a full register or FIFO, then the AXI write transaction completes with an error condition.
Reading to the SPIDTR is not allowed and the read transaction results in undefined data.
X-Ref Target - Figure 5
Tx Data ((D(N-1) - D0))
N-1
0
Figure 5: SPI Data Transmit Register (C_BASEADDR + 0x68)
Table 8: SPI Data Transmit Register (SPIDTR) Description (C_BASEADDR + 0x68)
Bit(s)
Name
Core Access Reset Value
Description
[N-1] - 0 Tx Data⁽¹⁾ (D_{N-1 -} D₀)
Write only
N-bit SPI transmit data. N can be 8, 16 or 32.
0
N = 8 when C_NUM_TRANSFER_BITS = 8
N = 16 when C_NUM_TRANSFER_BITS = 16
N = 32 when C_NUM_TRANSFER_BITS = 32
1. The D_N-1 bit always represents the MSB bit irrespective of "LSB first" or "MSB first" transfer selection. When
C_NUM_TRANSFER_BITS = 8 or 16, the unused upper bits ((C_AXI_DATA_WIDTH-1) to N) are reserved.
SPI Data Receive Register (SPIDRR)
This register is used to read data that is received from the SPI bus. This is a double-buffered register. The received
data is placed in this register after each complete transfer. The SPI architecture does not provide any means for a
slave to throttle traffic on the bus; consequently, the SPIDRR is updated following each completed transaction only
if the SPIDRR was read prior to the last SPI transfer. If the SPIDRR was not read, and therefore is full, the most
recently transferred data is lost and a receive overrun interrupt occurs. The same condition can occur with a master
SPI device as well.
For both master and slave SPI devices with a receive FIFO, the data is buffered in the FIFO. The receive FIFO is a
read-only buffer. If an attempt to read an empty receive register or FIFO is made, then the AXI read transaction
completes successfully with undefined data. Writes to the SPIDRR do not modify the register contents and return
with a successful OK response. The SPIDRR is shown in Figure 6, while the specifics of the data format is described
Table 9.
X-Ref Target - Figure 6
Rx Data (D(N-1) - D0)
N-1
0
Figure 6: SPI Data Receive Register (C_BASEADDR + 0x6C)
DS742 January 18, 2012
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Product Specification