DS742 Datasheet, PDF (16/33 Pages) Xilinx, Inc – Programable clock phase and polarity

LogiCORE IP AXI Serial Peripheral Interface (AXI SPI) (v1.02.a)
Table 15: IP Interrupt Enable Register (IPIER) Description (C_BASEADDR + 0x28) (Cont’d)
Bit(s)
Name
Access
Reset
Value
Description
Slave Mode-Fault Error Flag
1
Slave MODF
R/W
0 0 = Disabled
1 = Enabled
Mode-Fault Error Flag
0
MODF
R/W
0 0 = Disabled
1 = Enabled
Design Description
SPI Device Features
In addition to the features listed in the Features section, the SPI device also includes the following standard features:
• Supports multi-master configuration within the Field Programmable Gate Array (FPGA) with separated _I,
_O, _T representation of 3-state ports.
• Works with N times 8-bit data characters in default configuration. The default mode implements manual
control of the SS output via data written to the SPISSR. This appears directly on the SS output when the master
is enabled. This mode can be used only with external slave devices. An optional operation where the SS output
is toggled automatically with each 8-bit character transfer by the master device can be selected via a bit in the
SPICR for SPI master devices.
• Multi-master environment supported (implemented with 3-state drivers and requires software arbitration for
possible conflict). See the SPI in Multi-Master Configuration section.
• Multi-slave environment supported (automatic generation of additional slave select output signals for the
master).
• Supports maximum SPI clock rates up to one-half of the AXI clock rate in master mode and one-fourth of the
AXI clock rate in slave modes. C_SCK_RATIO = 2 is not supported in Slave Mode (due to the synchronization
method used between the AXI and SPI clocks). It is required to take care of the AXI and external clock signals
alignment when configured in slave mode.
• Parameterizable baud rate generator.
• The Write Collision error (WCOL) flag is not supported as a write collision error as described in the M68HC11
reference manual. The user must not write to the transmit register when an SPI data transfer is in progress.
• Back-to-back transactions are supported, which means there can be multiple byte/half-word/word transfers
taking place without interruption, provided that the transmit FIFO never gets empty and the receive FIFO
never gets full.
• All SPI transfers are full-duplex where an 8-bit data character is transferred from the master to the slave and an
independent 8-bit data character is transferred from the slave to the master. This can be viewed as a circular
16-bit shift register; an 8-bit shift register in the SPI master device and another 8-bit shift register in a SPI slave
device that are connected.
• This IP cannot be used for FPGA bitstream programming through the SPI interface during power-on reset
state.
• The data transfer and registering mechanism of this core is synchronized with the AXI clock. User should take
care while configuring the IP. See the timing parameters for the targeted device while configuring the core and
the C_SCK_RATIO parameter.
DS742 January 18, 2012
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Product Specification