DS742 Datasheet, PDF (14/33 Pages) Xilinx, Inc – Programable clock phase and polarity

LogiCORE IP AXI Serial Peripheral Interface (AXI SPI) (v1.02.a)
Table 14: IP Interrupt Status Register (IPISR) Description (C_BASEADDR + 0x20) (Cont’d)
Bit(s) Name
Access
Reset
Value
Description
Data Receive Register/FIFO Full
IPISR bit(4) is the data receive register full interrupt. Without FIFOs, this bit is set at
the end of an SPI element (An element can be a byte, half-word or word depending
4
DRR Full R/TOW⁽¹⁾ 0 on the value of C_NUM_TRANSFER_BITS generic) transfer by a one-clock period
strobe to the interrupt register. With FIFOs, this bit is set at the end of the SPI
element transfer when the receive FIFO has been filled by a one-clock period strobe
to the interrupt register.
Data Transmit Register/FIFO Underrun
IPISR bit(3) is the data transmit register/FIFO underrun interrupt. This bit is set at the
3
DTR Under
run
R/TOW⁽¹⁾
0
end of an SPI element transfer by a one-clock period strobe to the interrupt register
when data is requested from an "empty" transmit register/FIFO by the SPI core logic
to perform an SPI transfer. This can occur only when the SPI device is configured as
a slave and is enabled by the SPE bit as set. All zeros are loaded in the shift register
and transmitted by the slave in an underrun condition.
Data Transmit Register/FIFO Empty
IPISR bit(2) is the data transmit register/FIFO empty interrupt. Without FIFOs, this
bit is set at the end of an SPI element transfer by a one-clock period strobe to the
interrupt register. With FIFOs, this bit is set at the end of the SPI element transfer
2 DTR Empty R/TOW⁽¹⁾ 0 _{when the transmit FIFO is emptied by a one-clock period strobe to the interrupt}
register. See section Transfer Ending Period. In the context of the M68HC11
reference manual, when configured without FIFOs, this interrupt is equivalent in
information content to the complement of the SPI transfer complete flag SPIF
interrupt bit. In master mode if this bit is set to 1, no more SPI transfers are permitted.
Slave Mode-Fault Error
1
Slave
MODF
R/TOW⁽¹⁾
0
IPISR bit(1) is the slave mode-fault error flag. This interrupt is generated if the SS
signal goes active while the SPI device is configured as a slave but is not enabled.
This bit is set immediately upon SS going active and continually set if SS is active
and the device is not enabled.
Mode-Fault Error
0
MODF R/TOW⁽¹⁾ 0 ^{IPISR bit(0) is the mode-fault error flag. This interrupt is generated if the SS signal}
goes active while the SPI device is configured as a master. This bit is set immediately
upon SS going active.
Notes:
1. TOW = Toggle On Write. Writing a 1 to a bit position within the register causes the corresponding bit position in the register to
toggle.
DS742 January 18, 2012
www.xilinx.com
14
Product Specification