DS742 Datasheet, PDF (7/33 Pages) Xilinx, Inc – Programable clock phase and polarity

LogiCORE IP AXI Serial Peripheral Interface (AXI SPI) (v1.02.a)
Table 4: Core Registers (Cont’d)
Base Address + Offset
(hex)
Register Name
Access
Type
Default Value
(hex)
Description
C_BASEADDR + 20
IPISR
R/TOW⁽²⁾
0x0
IP Interrupt Status Register
C_BASEADDR + 28
IPIER
R/W
0x0
IP Interrupt Enable Register
Note:
1. Exists only when C_FIFO_EXIST = 1.
2. TOW = Toggle On Write. Writing a 1 to a bit position within the register causes the corresponding bit position in the register to
toggle.
Register Details
Software Reset Register (SRR)
The Software Reset Register allows the programmer to reset the core independent of other cores in the systems. To
activate software generated reset, the value of 0x0000_000A must be written to this register. Any other write access
generates an error condition with undefined results and results in error generation. The bit assignment in the
software reset register is shown in Figure 2 and described in Table 5. An attempt to read this register returns
undefined data.
X-Ref Target - Figure 2
31
0
Reset
Figure 2: Software Reset Register (C_BASEADDR + 0x40)
DS742_02
Table 5: Software Reset Register (SRR) Description (C_BASEADDR + 0x40)
Bit(s) Name
Core
Access
Reset
Value
Description
31 - 0 Reset Write only N/A The only allowed operation on this register is a write of 0x0000000A, which resets the AXI
SPI IP core.
SPI Control Register (SPICR)
The SPI Control Register (SPICR) gives the programmer control over various aspects of the AXI SPI IP core. The bit
assignment in the SPICR is shown in Figure 3 and described in Table 6.
X-Ref Target - Figure 3
Master
TransactionRx ^FIFO
Master
Inhibit ^{Reset CPHA}
LOOP
31
10 9 8 7 6 5 4 3 2 1 0
Reserved
LSB First
Tx FIFO
Reset
Manual Slave ^CPOL
Select Assertion
Enable
Figure 3: SPI Control Register (C_BASEADDR + 0x60)
SPE
DS742_03
DS742 January 18, 2012
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Product Specification