DS742 Datasheet, PDF (24/33 Pages) Xilinx, Inc – Programable clock phase and polarity

LogiCORE IP AXI Serial Peripheral Interface (AXI SPI) (v1.02.a)
3. Write configuration data to master SPI device SPICR as required.
4. Write configuration data to slave SPI device SPICR as required.
5. Write the active Low, one-hot encoded slave select address to the master SPISSR.
6. Write data to slave SPIDTR register as required.
7. Write data to master SPIDTR register to start transfer.
8. Wait for interrupt (typically IPISR bit(4)) or poll status for completion.
9. Read IPISR of both master and slave SPI devices as required.
10. Perform interrupt requests as required.
11. Read SPISR of both master and slave SPI devices as required.
12. Perform actions as required or dictated by SPISR data.
SPI master and slave devices where registers/FIFOs are filled before SPI transfer is started and multiple
discrete 8-bit transfers are performed (optional mode)
User can follow the subsequent steps to successfully complete an SPI transaction:
1. Start from proper state including SPI bus arbitration.
2. Configure master DGIER and IPIER. Also configure slave DGIER and IPIER registers as desired.
3. Write configuration data to master SPI device SPICR as required.
4. Write configuration data to slave SPI device SPICR as required.
5. Write the active Low, one-hot encoded slave select address to the master SPISSR.
6. Write all data to slave SPIDTR Register/FIFO as required.
7. Write all data to master SPIDTR Register/FIFO.
8. Write enable bit to master SPICR which starts transfer.
9. Wait for interrupt (typically IPISR bit(4)) or poll status for completion.
10. Read IPISR of both master and slave SPI devices as required.
11. Perform interrupt requests as required.
12. Read SPISR of both master and slave SPI devices as required.
13. Perform actions as required or dictated by SPISR data.
SPI master and slave devices with FIFOs where some initial data is written to FIFOs, the SPI transfer is
started, data is written to the FIFOs as fast or faster than the SPI transfer and multiple discrete 8-bit
transfers are performed (optional mode).
The user can follow the subsequent steps to successfully complete an SPI transaction:
1. Start from proper state including SPI bus arbitration.
2. Configure master DGIER and IPIER. Also configure slave DGIER and IPIER registers as desired.
3. Write configuration data to master SPI device SPICR as required.
4. Write configuration data to slave SPI device SPICR as required.
5. Write the active Low, one-hot encoded slave select address to the master SPISSR.
6. Write initial data to slave transmit FIFO as required.
7. Write initial data to master transmit FIFO.
8. Write enable bit to master SPICR which starts transfer.
9. Continue writing data to both master and slave FIFOs.
10. Wait for interrupt (typically IPISR bit(4)) or poll status for completion.
DS742 January 18, 2012
www.xilinx.com
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Product Specification