DS742 Datasheet, PDF (15/33 Pages) Xilinx, Inc – Programable clock phase and polarity

LogiCORE IP AXI Serial Peripheral Interface (AXI SPI) (v1.02.a)
IP Interrupt Enable Register (IPIER)
The interrupt controller IPIER register allows the system interrupt output to be active. This interrupt is generated if
the enabled bit in IPIER detects any activity on the corresponding IPISR bit. The IPIER has an enable bit for each
defined bit of the IPISR as shown in Figure 12 and described in Table 15. All bits are cleared upon reset.
X-Ref Target - Figure 12
Reserved
DRR
DRR_Not_Empty
Full
Tx FIFO
DTR
Half Empty
Empty MODF
31
987654 321 0
DRR
Slave
Over-run
MODF
Slave
DTR
Mode_Select ^Under-run
DS742_12
Figure 12: IP Interrupt Enable Register (IPIER) (C_BASEADDR + 0x28)
Table 15: IP Interrupt Enable Register (IPIER) Description (C_BASEADDR + 0x28)
Bit(s)
Name
Access
Reset
Value
Description
31 - 9
Reserved
N/A N/A Reserved
8 DRR_Not_Empty R/W
DRR_Not_Empty
0 = Disabled
1 = Enabled
0
Note: The setting of this bit is applicable only when C_FIFO_EXIST = 1 and
the core is configured in slave mode.
If C_FIFO_EXIST = 0, setting of this bit has no effect, which means that this
bit is not set in IPIER. Therefore, it is recommended to use this bit only in
C_FIFO_EXIST = 1 condition when the core is configured in slave mode.
7 Slave_Select_Mode R/W
Slave_Select_Mode
0 = Disabled
0 1 = Enabled
This bit is applicable only when the core is configured in slave mode. In master
mode, setting this bit has no effect.
6 Tx FIFO Half Empty R/W
Transmit FIFO Half Empty
0 = Disabled
0 ^{1 = Enabled}
Note: This bit is meaningful only if the AXI SPI IP core is configured with
FIFOs.
Receive FIFO Overrun
5
DRR Overrun
R/W
0 0 = Disabled
1 = Enabled
Data Receive Register/FIFO Full
4
DRR Full
R/W
0 0 = Disabled
1 = Enabled
Data Transmit FIFO Underrun
3
DTR Underrun
R/W
0 0 = Disabled
1 = Enabled
Data Transmit Register/FIFO Empty
2
DTR Empty
R/W
0 0 = Disabled
1 = Enabled
DS742 January 18, 2012
www.xilinx.com
15
Product Specification