DS742 Datasheet, PDF (6/33 Pages) Xilinx, Inc – Programable clock phase and polarity

LogiCORE IP AXI Serial Peripheral Interface (AXI SPI) (v1.02.a)
Parameters - I/O Signal Dependencies
The dependencies between the AXI SPI IP core design parameters and I/O signals are described in Table 3.
Table 3: Parameters - Signal Dependencies
Generic
or Port
Name
Affects Depends
Relationship Description
Design Parameters
G4 C_S_AXI_ADDR_WIDTH
P3, P13
-
Affects the number of bits in address bus
G5 C_S_AXI_DATA_WIDTH
P6, P7, P16
Affects the number of bits in data bus
G8 C_NUM_SS_BITS
P31, P32
-
Defines the total number of slave select bits
I/O Signals
P3
S_AXI_AWADDR[(C_S_AXI_ADDR_
WIDTH - 1) : 0]
-
G4
Width of the AXI bus address varies with
C_S_AXI_ADDR_WIDTH.
P6
S_AXI_WDATA[(C_S_AXI_
DATA_WIDTH - 1) : 0]
-
G5
Width of the S_AXI_WDATA varies according to
C_S_AXI_DATA_WIDTH.
P7
S_AXI_WSTB[((C_S_AXI_
DATA_WIDTH/8) - 1): 0]
-
G5
Width of the S_AXI_WSTB varies according to
C_S_AXI_DATA_WIDTH.
P16
S_AXI_RDATA[(C_S_AXI_DATA_
WIDTH - 1):0]
-
G5
Width of the S_AXI_RDATA varies according to
C_S_AXI_DATA_WIDTH.
P31 SS_I[(C_NUM_SS_BITS - 1):0]
-
G8
The number of SS_I pins are generated based on
C_NUM_SS_BITS.
P32 SS_O[(C_NUM_SS_BITS - 1):0]
-
G8
The number of SS_O pins are generated based
on C_NUM_SS_BITS.
Register Overview Table
Table 4 gives a summary of the AXI SPI IP core registers. The Transmit FIFO Occupancy Register and the Receive
FIFO Occupancy Register exist only when C_FIFO_EXIST = 1.
Table 4: Core Registers
Base Address + Offset
(hex)
Register Name
Access
Type
Default Value
(hex)
Description
Core Grouping
C_BASEADDR + 40
SRR
Write
N/A
Software Reset Register
C_BASEADDR + 60
SPICR
R/W
0x180
SPI Control Register
C_BASEADDR + 64
SPISR
Read
0x25
SPI Status Register
C_BASEADDR + 68
SPIDTR
Write
0x0
SPI Data Transmit Register
A single register or a FIFO
C_BASEADDR + 6C
SPIDRR
Read
NA
SPI Data Receive Register
A single register or a FIFO
C_BASEADDR + 70
SPISSR
R/W No slave is selected SPI Slave Select Register
C_BASEADDR + 74
SPI Transmit FIFO
Occupancy Register ⁽¹⁾
Read
0x0
Transmit FIFO Occupancy Register
C_BASEADDR + 78
SPI Receive FIFO
Occupancy Register⁽¹⁾
Read
0x0
Receive FIFO Occupancy Register
Interrupt Controller Grouping
C_BASEADDR + 1C
DGIER
R/W
0x0
Device Global Interrupt Enable Register
DS742 January 18, 2012
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Product Specification