DS742 Datasheet, PDF (22/33 Pages) Xilinx, Inc – Programable clock phase and polarity

LogiCORE IP AXI Serial Peripheral Interface (AXI SPI) (v1.02.a)
The master transfer inhibit (SPICR bit(8)) can be used to inhibit master transactions until the slave select is asserted
manually and all data registers of FIFOs are initialized as required. This can be used before the first transaction and
after any transaction that is allowed to complete. When the preceding rules are followed, the timing is the same as
presented for the automatic slave select assertion mode with the exception that assertion of the slave select signal
and the number of elements transferred is controlled by the user.
Beginning and Ending SPI Transfers
The details of the beginning and ending periods depend on the CPHA format selected and whether the SPI is
configured as a master or a slave. The following sections describe the beginning and ending period for SPI transfers.
Transfer Beginning Period
The definition of the transfer beginning period for the AXI SPI IP core is consistent with the M68HC11 reference
manual. This manual can be referenced for more details. All SPI transfers are started and controlled by a master SPI
device. As a slave, the processor considers a transfer to begin with the first SCK edge or the falling edge of SS,
depending on the CPHA format selected. When CPHA equals zero, the falling edge of SS indicates the beginning of
a transfer. When CPHA equals one, the first edge on the SCK indicates the start of the transfer. In either CPHA
format, a transfer can be aborted by deasserting the SS(N) signal. This causes the SPI slave logic and bit counters to
be reset. In this implementation, the software driver can deselect all slaves (that is, SS(N) is driven high) to abort a
transaction. Although the hardware is capable of changing slaves during the middle of a single or burst transfer, it
is recommended that the software be designed to prevent this.
In slave configuration, the data is transmitted from the SPIDTR register on the first AXI rising clock edge following
SS signal being asserted. The data should be available in the register or FIFO. If data is not available, then the
underrun interrupt is asserted.
Transfer Ending Period
The definition of the transfer ending period for the AXI SPI IP core is consistent with the M68HC11 reference
manual. The SPI transfer is signaled complete when the SPIF flag is set. However, depending on the configuration
of the SPI system, there might be additional tasks to be performed before the system can consider the transfer
complete.
When configured without FIFOs, the Rx_Full bit, bit(1) in the SPISR is set to denote the end of a transfer. When data
is available in the SPIDRR register, bit(4) of the IPISR is asserted as well. The data in the SPIDRR is sampled on the
same clock edge as the assertion of the SPIDRR register Full interrupt.
When the SPI device is configured as a master without FIFOs, the following occurs:
• Rx_Empty bit, bit(0) and Tx_Full bit, bit(3) in the SPISR are cleared.
• Tx_Empty bit, bit(2) and Rx_Full bit, bit(1) in SPISR are set.
• DRR Full bit, bit(4) and Slave MODF bit, bit(1) in the IPISR are set on the first rising AXI clock edge after the
end of the last SCK cycle.
The end of the last SCK cycle is a transition on SCK for CPHA = 0, but is not denoted by a transition on SCK for
CPHA = 1. See Figure 14 and Figure 15. However, the internal master clock provides this SCK edge which prompts
the setting/clearing of the bits noted.
In this design, a counter was implemented which allows the simultaneous setting of SPISR and IPISR bits for both
master and slave SPI devices. External SPI slave devices can use an internal clock that is asynchronous to the SCK
clock. This can cause status bits in the SPISR and IPISR to be inconsistent with each other. Therefore, the AXI SPI IP
core cannot be used with external slave devices that do not use the AXI clock.
DS742 January 18, 2012
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Product Specification