DS742 Datasheet, PDF (3/33 Pages) Xilinx, Inc – Programable clock phase and polarity

LogiCORE IP AXI Serial Peripheral Interface (AXI SPI) (v1.02.a)
The core can communicate with both off-chip and on-chip masters and slaves. The number of slaves is limited to 32
by the size of the Slave Select Register. However, the number of slaves and masters does impact the achievable
performance in terms of frequency and resource utilization. All of the SPI and INTR registers are 32-bit wide. The
core supports only 32-bit word access to all SPI and INTR register modules.
AXI4-Lite IP IPIF Interface (IPIF): The AXI4-Lite IP Interface (IPIF) provides the interface to the AXI4-Lite to IP
Interconnect (IPIC). The read and write transactions at the AXI4-Lite interface are translated into equivalent IP
Interconnect (IPIC) transactions. See [Ref 4] for more information about the IPIC.
SPI Register Module: The SPI Register Module includes all memory mapped registers (as shown in Figure 1). It
interfaces to the AXI. It consists of Status Register, Control Register, N-bit Slave Select Register (N ≤ 32) and a pair
of Transmit/Receive Registers.
Interrupt Controller Register set Module: The Interrupt Controller Register set Module consists of interrupt
related registers, namely: Device Global Interrupt Enable Register (DGIER), IP Interrupt Enable Register (IPIER),
and IP Interrupt Status Register (IPISR).
SPI Module: The SPI Module consists of a shift register, a parameterized baud rate generator (BRG) and a control
unit. It provides the SPI interface, including the control logic and initialization logic. It is the heart of core.
Optional FIFOs: The Tx FIFO and Rx FIFO are implemented on both transmit and receive paths when enabled by
the parameter C_FIFO_EXIST. The width of Tx FIFO and Rx FIFO are the same and depend on the generic
C_NUM_TRANSFER_BITS. When the FIFOs are enabled, their depth is fixed at 16.
Design Parameters
To allow the user to obtain an AXI SPI IP core that is uniquely tailored for the system, certain features can be
parameterized. Parameterization affords a measure of control over the function, resource usage, and performance
of the implemented AXI SPI IP core. The features that can be parameterized are as shown in Table 1. In addition to
the parameters listed in this table, there are also parameters that are inferred for each AXI interface in the
Embedded Development Kit (EDK) tools. Through the design, these EDK-inferred parameters control the behavior
of the AXI Interconnect. For a complete list of the interconnect settings related to the AXI interface, see [Ref 6].
Table 1: Design Parameters
Generic
Feature/Description
G1 Target FPGA family
G2 AXI Base Address
Parameter Name
System Parameters
C_FAMILY
AXI Parameters
C_BASEADDR
Allowable Values
virtex6 , spartan6,
7series, zynq
Valid Address⁽¹⁾
G3 AXI High Address
C_HIGHADDR
Valid Address⁽¹⁾
G4 AXI Address Bus Width
C_S_AXI_ADDR_WIDTH
32
G5 AXI Data Bus Width
C_S_AXI_DATA_WIDTH
32, 64
AXI SPI IP Core Parameters
G6 Include receive and transmit FIFOs C_FIFO_EXIST
0 = FIFOs not
included
1 = FIFOs included
Default
Value
VHDL
Type
virtex6
string
None⁽²⁾
None⁽²⁾
32
32
std_logic_
vector
std_logic_
vector
integer
integer
1
integer
DS742 January 18, 2012
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Product Specification