DS742 Datasheet, PDF (2/33 Pages) Xilinx, Inc – Programable clock phase and polarity

LogiCORE IP AXI Serial Peripheral Interface (AXI SPI) (v1.02.a)
Functional Description
The top level block diagram for the Xilinx^® AXI SPI IP core is shown in Figure 1.
X-Ref Target - Figure 1
AXI SPI
SPI Module
AXI4-Lite
Interface
Module
Interrupt
Register
Module
Status Register
(SPISR)
Control Register
(SPICR)
Slave Select Register
(SPISSR)
Transmit Register
(SPIDTR)
Receive Register
(SPIDRR)
Interrrupt Controller
Register Set
(1)
Tx FIFO
(1)
Rx FIFO
(3)
BRG
Shift
Register
Pins
Interface
Control Unit
SPI
Ports
SCK
MISO
MOSI
SS(N)
(2)
SPISEL
Notes:
1. The width of Tx FIFO, Rx FiFO, and Shift Register depends on the value of the generic, C_NUM_TRANSER_BITS.
2. The width of SS depends on the value of the generic C_NUM_SS_BITS.
3. BRG (Buad Rate Generator)
Figure 1: AXI SPI IP Core Top-Level Block Diagram
DS742_01
The AXI SPI IP core is a full-duplex synchronous channel that supports a four-wire interface (receive, transmit,
clock and slave-select) between a master and a selected slave. The core supports Manual Slave Select Mode as the
default mode of operation. This mode allows the user to manually control the slave select line using the data written
to the slave select register. This allows transfers of an arbitrary number of elements without toggling the slave select
line between elements. However, the user must toggle the slave select line before starting a new transfer.
The other mode of operation is Automatic Slave Select Mode. In this mode the slave select line is toggled
automatically after each element transfer. This mode is described in more detail in SPI Protocol with Automatic
Slave Select Assertion.
The AXI SPI IP core supports continuous transfer mode; when configured as a master the transfer continues until
the data is available in transmit register/FIFO. This capability is provided in both manual and automatic slave
select modes.
When the core is configured as a slave and if inadvertently its slave select line (SPISEL) goes high (inactive state) in
between the data element transfer, then the current transfer is aborted. Again if the slave select line goes low then
the aborted data element is transmitted again. The core allows additional slaves to be added with automatic
generation of the required decoding logic for individual slave select outputs by the master. Additional masters can
also be added. However, the means to detect all possible conflicts are not implemented with this interface standard.
To eliminate conflicts, software is required to arbitrate bus control.
DS742 January 18, 2012
www.xilinx.com
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Product Specification