DS742 Datasheet, PDF (5/33 Pages) Xilinx, Inc – Programable clock phase and polarity

LogiCORE IP AXI Serial Peripheral Interface (AXI SPI) (v1.02.a)
Table 2: I/O Signal Descriptions (Cont’d)
Port
Signal Name
Interface
I/O
Initial
State
Description
P11 S_AXI_BVALID
AXI
O
0
Write response valid. This signal indicates that a valid write
response is available.
P12 S_AXI_BREADY
AXI
I
-
Response ready. This signal indicates that the master can
accept the response information.
AXI Read Address Channel Signals
P13
S_AXI_ARADDR[(C_S_AXI_
ADDR_WIDTH - 1) : 0 ]
AXI
I
-
Read address. The read address bus gives the address of
a read transaction.
P14 S_AXI_ARVALID
Read address valid. When HIGH, this signal indicates that
AXI
I
-
the read address and control information is valid and
remains stable until the address acknowledgement signal,
S_AXI_ARREADY, is high.
P15 S_AXI_ARREADY
AXI
O
1
Read address ready. This signal indicates that the slave is
ready to accept an address and associated control signals.
AXI Read Data Channel Signals
P16
S_AXI_RDATA[(C_S_AXI_
DATA_WIDTH - 1) : 0]
AXI O 0 Read data
P17 S_AXI_RRESP[1 : 0]
Read response. This signal indicates the status of the read
transfer.
AXI O 0 00 - OKAY (normal response)
10 - SLVERR (error condition)
11 - DECERR (not issued by core)
P18 S_AXI_RVALID
AXI
O
0
Read valid. This signal indicates that the required read data
is available and the read transfer can complete.
P19 S_AXI_RREADY
AXI
I
-
Read ready. This signal indicates that the master can
accept the read data and response information.
SPI Interface Signals
P20 IP2INTC_Irpt
SPI O 0 Interrupt control signal from SPI
P21 SCK_I
SPI
I - SPI bus clock input
P22 SCK_O
SPI O 0 SPI bus clock output
P23 SCK_T
SPI O 1 3-state enable for SPI bus clock.Active Low
P24 MOSI_I
SPI
I
- Master output slave input
P25 MOSI_O
SPI O 1 Master output slave input
P26 MOSI_T
SPI O 1 3-state enable master output slave input. Active Low.
P27 MISO_I
SPI
I - Master input slave output
P28 MISO_O
SPI O 1 Master input slave output
P29 MISO_T
SPI O 1 3-state enable master input slave output. Active Low.
P30 SPISEL⁽¹⁾
SPI
I
1
Local SPI slave select active Low input
Must be set to 1 in idle state
P31 SS_I[(C_NUM_SS_BITS - 1):0]
SPI
I
-
Input one-hot encoded. This signal is a dummy signal and
is used in the design as chip-select input.
P32 SS_O[(C_NUM_SS_BITS - 1):0] SPI
O
1
Output one-hot encoded, active Low slave select vector of
length n.
P33 SS_T
SPI O 1 3-state enable for slave select. Active Low.
1. SPISEL signal is used as a slave select line when AXI SPI is configured as a slave.
DS742 January 18, 2012
www.xilinx.com
5
Product Specification