DS742 Datasheet, PDF (4/33 Pages) Xilinx, Inc – Programable clock phase and polarity

LogiCORE IP AXI Serial Peripheral Interface (AXI SPI) (v1.02.a)
Table 1: Design Parameters (Cont’d)
Generic
Feature/Description
Parameter Name
G7 SPI clock frequency ratio
C_SCK_RATIO
G8 Total number of slave select bits C_NUM_SS_BITS
G9 Select number of transfer bits as 8 C_NUM_TRANSFER_BITS
Allowable Values
2⁽³⁾, 4, 8, Nx16 for
N = 1, 2, 3, ...
1 - 32
8, 16, 32
Default
Value
32
1
8
VHDL
Type
integer
integer
integer
Notes: Notes:
1. The range C_BASEADDR to C_HIGHADDR is the address range for the AXI SPI IP. This range is subject to restrictions to
accommodate the simple address decoding scheme that is employed. The size, C_HIGHADDR - C_BASEADDR + 1, must be a
power of two and must be at least 0x80 to accommodate all AXI SPI IP core registers. However, a larger power of two can be
chosen to reduce decoding logic. C_BASEADDR must be aligned to a multiple of the range size.
2. No default value is specified to ensure that an actual value appropriate to the system is set. The values must be set by the user.
3. C_SCK_RATIO = 2 is not supported when the AXI SPI IP core is configured as slave. Read the Precautions to be Taken while
Assigning the C_SCK_RATIO Parameter section carefully when using this parameter.
Input/Output (I/O) Signals
The I/O signals are listed and described in Table 2.
Table 2: I/O Signal Descriptions
Port
Signal Name
P1 S_AXI_ACLK
P2 S_AXI_ARESETN
P3
S_AXI_AWADDR[(C_S_AXI_
ADDR_WIDTH - 1) : 0]
P4 S_AXI_AWVALID
P5 S_AXI_AWREADY
P6
S_AXI_WDATA[(C_S_AXI_
DATA_WIDTH - 1) : 0]
P7
S_AXI_WSTB[((C_S_AXI_
DATA_WIDTH/8) - 1) : 0]
P8 S_AXI_WVALID
P9 S_AXI_WREADY
P10 S_AXI_BRESP[1 : 0]
Interface
I/O
Initial
State
Description
AXI Global System Signals
AXI
I - AXI Clock
AXI
I - AXI Reset, active Low
AXI Write Address Channel Signals
AXI
I
-
AXI Write address. The write address bus gives the address
of the write transaction.
AXI
I
-
Write address valid. This signal indicates that a valid write
address and control information are available.
AXI
O
0
Write address ready. This signal indicates that the slave is
ready to accept an address and associated control signals.
AXI Write Channel Signals
AXI
I - Write data
AXI
I
-
Write strobes. This signal indicates which byte lanes to
update in memory.
AXI
I
-
Write valid. This signal indicates that valid write data and
strobes are available.
AXI
O
0
Write ready. This signal indicates that the slave can accept
the write data.
AXI Write Response Channel Signals
Write response. This signal indicates the status of the write
transaction
AXI O 0 00 - OKAY (normal response)
10 - SLVERR (error response)
11 - DECERR (not issued by core)
DS742 January 18, 2012
www.xilinx.com
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Product Specification