DS742 Datasheet, PDF (19/33 Pages) Xilinx, Inc – Programable clock phase and polarity

LogiCORE IP AXI Serial Peripheral Interface (AXI SPI) (v1.02.a)
Underrun and overrun conditions error detection is also provided. Underrun conditions can happen only in slave
mode operation. This happens when a master commands a transfer but the slave does not have data in the transmit
register or FIFO for transfer. In this case, the slave underrun interrupt is asserted and the slave shift register is
loaded with all zeros for transmission. Overrun can happen to both master and slave devices where a transfer
occurs when the receive register or FIFO is full. During an overrun condition, the data received in that transfer is not
registered (it is lost) and the IPISR overrun interrupt bit(5) is asserted.
Precautions to be Taken while Assigning the C_SCK_RATIO Parameter
The AXI SPI IP core is tested in hardware with the SPI slave devices like serial EEPROMs, ATMEL,
STMicro-Electronics and Intel flash memories. Read the data sheet of the targeted SPI slave flash memory or
EEPROMs for maximum speed of operation. It is the responsibility of the user to mention the correct values while
deciding the AXI clock and selecting the C_SCK_RATIO parameter of the core. The AXI clock and the
C_SCK_RATIO decide the clock at SCK pin of AXI SPI IP core. While using different external SPI slave devices, the
C_SCK_RATIO should be set carefully and the maximum clock frequencies supported by all the external SPI slave
devices should be taken into account.
SPI Slave Mode
The AXI SPI core can be configured in the slave mode by connecting the external master’s slave select line to SPISEL
and by setting bit 2 of SPI Control Register (SPICR) to '0'. All the incoming signals are synchronized to the AXI when
C_SCK_RATIO > 4. Due to the tight timing requirements when C_SCK_RATIO = 4 the incoming SCK clock signal
and its synchronized signals are used directly in the internal logic. Therefore it is required that the external clock be
synchronized with the AXI clock when C_SCK_RATIO = 4. For other C_SCK_RATIO values, it is preferred, but
might not be necessary, to have such synchronization.
During the slave mode operation it is strongly recommended to use the FIFO by setting C_FIFO_EXIST = 1. In the
slave mode, two new interrupts are available in IPISR DRR_Not_Empty - bit 8 and Slave_Mode_Select - bit 7 along
with the available interrupts. Before other SPI master starts communication, it is mandatory to fill the slave core
transmit FIFO with the required data beats. After the master starts communication, with the core configured in
slave mode, the core will transfer data until the data exists in its transmit FIFO. At the end of last data beat
transmitted from slave FIFO, the core (in slave mode) generates the DTR Empty signal to notify that new data beats
needed to be filled in its transmit FIFO before further communication is started.
SPI Transfer Formats
SPI Clock Phase and Polarity Control
Software can select any of four combinations of serial clock (SCK) phase and polarity with programmable bits in the
SPICR. The clock polarity (CPOL) bit selects an active High (the clock’s idle state = low) or active Low clock (the
clock’s idle state = high). Determination of whether the edge of interest is the rising or falling edge depends on the
idle state of the clock (that is, CPOL setting).
The clock phase (CPHA) bit can be set to select one of two different transfer formats. If CPHA = 0, data is valid on
the first SCK edge (rising or falling) after SS(N) has been asserted. If CPHA = 1, data is valid on the second SCK
edge (rising or falling) after SS(N) has asserted. For successful transfers the clock phase and polarity must be
identical for the master SPI device and the selected slave device.
The first SCK cycle begins with a transition of SCK signal from its idle state and this denotes the start of the data
transfer. Because the clock transition from idle denotes the start of a transfer, the M68HC11 specification notes that
DS742 January 18, 2012
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Product Specification