DS742 Datasheet, PDF (11/33 Pages) Xilinx, Inc – Programable clock phase and polarity

LogiCORE IP AXI Serial Peripheral Interface (AXI SPI) (v1.02.a)
Table 9: SPI Data Receive Register (SPIDRR) Description (C_BASEADDR + 0x6C)
Bit(s)
Name
Core Access Reset Value
Description
[N-1] - 0 Rx Data⁽¹⁾ (D_{N-1 -} D₀)
Read only
N-bit SPI receive data. N can be 8, 16 or 32.
0
N = 8 when C_NUM_TRANSFER_BITS = 8
N = 16 when C_NUM_TRANSFER_BITS = 16
N = 32 when C_NUM_TRANSFER_BITS = 32
1. The D_N-1 bit always represents the MSB bit irrespective of "LSB first" or "MSB first" transfer selection. When
C_NUM_TRANSFER_BITS = 8 or 16, the unused upper bits ((C_AXI_DATA_WIDTH-1) to N) are reserved.
SPI Slave Select Register (SPISSR)
This register contains an active Low, one-hot encoded slave select vector SS of length N, where N is the number of
slaves set by parameter C_NUM_SS_BITS. The SS occupies the right-most bits of the register. At most, one bit can
be asserted low. This bit denotes the slave with whom the local master communicates. The bit assignment in the
SPISSR is shown in Figure 7 and described in Table 10.
X-Ref Target - Figure 7
Reserved
Selected Slave
31
N N-1
0
DS742_07
Figure 7: SPI Slave Select Register (C_BASEADDR + 0x70)
Table 10: SPI Slave Select Register (SPISSR) Description (C_BASEADDR + 0x70)
Bit(s) Name Core Access Reset Value
Description
31 - N Reserved
N/A
N/A
Reserved
[N-1] - 0
Selected
Slave
R/W
Active Low, one-hot encoded slave select vector of length N-bits. N
1
must be less than or equal to the data bus width (32-bit). The slaves are
numbered right to left starting at zero with the LSB. The slave numbers
correspond to the indexes of signal SS.
SPI Transmit FIFO Occupancy Register (Tx_FIFO_OCY)
The SPI Transmit FIFO Occupancy Register is present only if the AXI SPI IP core is configured with FIFOs
(C_FIFO_EXIST = 1). If it is present and if the Transmit FIFO is not empty, the register contains a four-bit,
right-justified value that is one less than the number of elements in the FIFO (occupancy minus one). This register
is read-only. A write to it (or a read when the FIFO is empty) does not affect the register contents. The only reliable
way to determine that the Tx FIFO is empty is by reading the Tx_Empty status bit in the SPI Status Register or the
Data Transmit Register (DTR) Empty bit in the Interrupt Status Register. The Transmit FIFO Occupancy register is
shown in Figure 8, while the specifics of the data format are described in Table 11.
X-Ref Target - Figure 8
Reserved
Occupancy
Value
31
43
0
Figure 8: SPI Transmit FIFO Occupancy Register (C_BASEADDR + 0x74)
Table 11: SPI Transmit FIFO Occupancy Register Description (C_BASEADDR + 0x74)
Bit(s)
Name
Core Access Reset Value (hex)
Description
31 - 4 Reserved
N/A
N/A
Reserved
3 - 0 Occupancy Value
Read
0
Bit 3 is the MSB. The binary value plus 1 yields the occupancy.
DS742 January 18, 2012
www.xilinx.com
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Product Specification