DS742 Datasheet, PDF (12/33 Pages) Xilinx, Inc – Programable clock phase and polarity

LogiCORE IP AXI Serial Peripheral Interface (AXI SPI) (v1.02.a)
SPI Receive FIFO Occupancy Register (Rx_FIFO_OCY)
The SPI Receive FIFO Occupancy Register is present if and only if the AXI SPI IP core is configured with FIFOs
(C_FIFO_EXIST = 1). If it is present and if the Receive FIFO is not empty, the register contains a four-bit,
right-justified value that is one less than the number of elements in the FIFO (occupancy minus one). This register
is read-only. A write to it (or of a read when the FIFO is empty) does not affect the register contents. The only reliable
way to determine that the Rx FIFO is empty is by reading the Rx_Empty status bit in the SPI Status Register. The
Receive FIFO Occupancy register is shown in Figure 9, while the specifics of the data format are described in
Table 12.
X-Ref Target - Figure 9
Reserved
Occupancy
Value
31
43
0
Figure 9: SPI Receive FIFO Occupancy Register (C_BASEADDR + 0x78)
DS742_09
Table 12: SPI Receive FIFO Occupancy Register Description (C_BASEADDR + 0x78)
Bit(s)
Name
Core Access Reset Value (hex)
Description
31- 4
Reserved
N/A
N/A
Reserved
3 - 0 Occupancy Value
Read
0
Bit 3 is the MSB. The binary value plus 1 yields the occupancy.
Interrupt Register Set Description
The AXI SPI IP core has a number of distinct interrupts that are sent to the interrupt controller submodule. The AXI
SPI IP interrupt controller allows each interrupt to be enabled independently (via the IP interrupt enable register
(IPIER)). The interrupt registers are in the interrupt controller. An interrupt strobe can be generated under multiple
conditions or only after a transfer completion. Setting the parameter C_FIFO_EXIST = 1 makes available almost all
of the interrupts shown in Table 14 when the core is configured in the master mode. Setting the parameter
C_FIFO_EXIST = 0 makes available all of the interrupts except bit(6), Tx FIFO Half Empty and bit(8) Data Receive
Register (DRR) Not Empty, which is not present in this case.
Device Global Interrupt Enable Register (DGIER)
The Device Global Interrupt Enable Register is used to globally enable the final interrupt output from the interrupt
controller as shown in Figure 10 and described in Table 13. This bit is a read/write bit and is cleared upon reset.
X-Ref Target - Figure 10
Reserved
31 30
0
DS742_10
Figure 10: Device Global Interrupt Enable Register (DGIER) (C_BASEADDR + 0x1C)
Table 13: Device Global Interrupt Enable Register(DGIER) Description (C_BASEADDR + 0x1C)
Bit(s) Name Access Reset Value
Description
31
GIE
R/W
Global Interrupt Enable
0
Enables all individually enabled interrupts to be passed to the interrupt controller.
0 = Disabled
1 = Enabled
30 - 0 Reserved N/A
N/A
Reserved
DS742 January 18, 2012
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Product Specification