DS742 Datasheet, PDF (8/33 Pages) Xilinx, Inc – Programable clock phase and polarity

LogiCORE IP AXI Serial Peripheral Interface (AXI SPI) (v1.02.a)
Table 6: SPI Control Register (SPICR) Description (C_BASEADDR + 0x60)
Bit(s)
Name
Core Reset
Access Value
Description
31 - 10 Reserved
N/A N/A Reserved
9
LSB First
R/W
0 LSB First
This bit selects LSB first data transfer format.
The default transfer format is MSB first.
0 = MSB first transfer format
1 = LSB first transfer format
Master
8 Transaction
Inhibit
Master Transaction Inhibit
This bit inhibits master transactions.
R/W
1 This bit has no effect on slave operation.
0 = Master transactions enabled
1 = Master transactions disabled
Manual Slave
7
Select
Assertion
R/W
Enable
Manual Slave Select Assertion Enable
This bit forces the data in the slave select register to be asserted on the slave
select output anytime the device is configured as a master and the device is
1 enabled (SPE asserted).
This bit has no effect on slave operation.
0 = Slave select output asserted by master core logic
1 = Slave select output follows data in slave select register
6 Rx FIFO Reset R/W
Receive FIFO Reset
When written to 1, this bit forces a reset of the Receive FIFO to the empty
0
condition. One AXI clock cycle after reset, this bit is again set to 0.
This bit is unassigned when the AXI SPI IP core is not configured with FIFOs.
0 = Receive FIFO normal operation
1 = Reset receive FIFO pointer
5 Tx FIFO Reset R/W
Transmit FIFO Reset
When written to 1, this bit forces a reset of the Transmit FIFO to the empty
0’
condition. One AXI clock cycle after reset, this bit is again set to 0.
This bit is unassigned when the AXI SPI IP core is not configured with FIFOs.
0 = Transmit FIFO normal operation
1 = Reset transmit FIFO pointer
Clock Phase (CPHA)
4
CPHA
R/W
0 _{Setting this bit selects one of two fundamentally different transfer formats.}
See SPI Clock Phase and Polarity Control.
Clock Polarity (CPOL)
3
CPOL
R/W
0
Setting this bit defines clock polarity.
0 = Active High clock; SCK idles low
1 = Active Low clock; SCK idles high
Master (SPI Master mode)
2
Master
R/W
0 ^{Setting this bit configures the SPI device as a master or a slave.}
0 = Slave configuration
1 = Master configuration
SPI System Enable
Setting this bit to 1 enables the SPI devices:
0 = SPI system disabled. Both master and slave outputs are in "3-state" and
1
SPE
R/W
0 slave inputs ignored.
1 = SPI system enabled. Master outputs active (for example, MOSI and SCK in
idle state) and slave outputs become active if SS becomes asserted. Master
starts a transfer when transmit data is available.
Local Loopback Mode
Enables local loopback operation and is functional only in master mode.
0
LOOP
R/W
0 ^{0 = Normal operation}
1 = Loopback mode. The transmitter output is internally connected to the
receiver input. The receiver and transmitter operate normally, except that
received data (from remote slave) is ignored.
DS742 January 18, 2012
www.xilinx.com
8
Product Specification