DS742 Datasheet, PDF (29/33 Pages) Xilinx, Inc – Programable clock phase and polarity

LogiCORE IP AXI Serial Peripheral Interface (AXI SPI) (v1.02.a)
X-Ref Target - Figure 16
MicroBlaze
Processor
Domain
MicroBlaze
Controller
(M_AXI_IC)
(M_AXI_DC)
AXI4 Memory
Map
Interconnect
AXI4 Memory Map
Domain
AXI DDR
Memory
Controller
AXI CDMA
Memory
D_LMB
I_LMB
(M_AXI_DP)
AXI4-Lite
Interconnect
Block RAM
Controller
Device Under
Test (DUT)
(Low Speed
Slave)
AXI INTC
AXI GPIO
LEDs
AXI UARTLite RS232
AXI4-Lite
Domain
MDM
Figure 16: Virtex-6 and Spartan-6 Devices F_MAX Margin System
DS742_16
Table 21: AXI SPI System Performance
Target FPGA
Target FMAX (MHz)
AXI-Lite
xc6slx45t ⁽¹⁾
90
xc6vlx240t ⁽²⁾
135
Target FMAX (MHz)
AXI4
120
180
Target F_MAX (MHz)
MicroBlaze ™
80
135
Notes:
1. S6 LUT utilization ~60%, block RAM utilization ~70%, I/O utilization 80%, MB not on AXI4 interconnect, AXI4 interconnect
configured with a single clock of 120MHz.
2. V6 LUT utilization ~70%, block RAM utilization ~70%, I/O utilization ~80%.
The target F_MAX is influenced by the exact system and is provided for guidance. It is not a guaranteed value across
all systems.
DS742 January 18, 2012
www.xilinx.com
29
Product Specification