DS742 Datasheet, PDF (17/33 Pages) Xilinx, Inc – Programable clock phase and polarity

LogiCORE IP AXI Serial Peripheral Interface (AXI SPI) (v1.02.a)
SPI in Multi-Master Configuration
The SPI bus to a given slave device (N-th device) consists of four wires, Serial Clock (SCK), Master Out Slave In
(MOSI), Master In Slave Out (MISO) and Slave Select (SS(N)). The signals SCK, MOSI and MISO are shared for all
slaves and masters. See Figure 13.
X-Ref Target - Figure 13
SPI Device 0
MOSI
MISO
SCK
SPISEL
SS(1)
SS(2)
SS(3)
SPI Device 1
MOSI
MISO
SCK
SPISEL
SS(1)
SS(2)
SS(3)
SS(0)
SS(1)
SS(2)
SS(3)
SPI Device 2
MOSI
MISO
SCK
SPISEL
SS(1)
SS(2)
SS(3)
SPI Device 3
MOSI
MISO
SCK
SPISEL
SS(1)
SS(2)
SS(3)
Slave-only devices (not shown) have only SPISEL local slave select ports
and do not have SS(N) remote slave select ports
DS742_13
Figure 13: Multi-Master Configuration Block Diagram
Each master SPI device has the functionality to generate an active Low, one-hot encoded SS(N) vector where each
bit is assigned an SS signal for each slave SPI device. It is possible for SPI master/slave devices to be both internal
to the FPGA and SPI slave devices to be external to the FPGA. SPI pins are automatically generated through Xilinx
Platform Generator when interfacing to an external SPI slave device. Multiple SPI master/slave devices are shown
in Figure 13.
Optional FIFOs
The user has the option to include FIFOs in the AXI SPI IP core as shown in Figure 1. Because SPI is full-duplex,
both transmit and receive FIFOs are instantiated as a pair.
When FIFOs are implemented, the slave select address is required to be the same for all data buffered in the FIFOs.
This is required because a FIFO for the slave select address is not implemented. Because burst mode is not
supported, both transmit and receive FIFOs are 16 elements deep and are accessed via single AXI transactions.
DS742 January 18, 2012
www.xilinx.com
17
Product Specification