DS712 Datasheet, PDF (9/61 Pages) Xilinx, Inc – LogiCORE IP AXI PLBv46 Bridge

LogiCORE IP AXI PLBv46 Bridge (v2.02.a)
Table 2: I/O Signal Description (Cont’d)
Port
Signal Name
Interface
I/O
Initial
State
Description
AXI Read Address Channel Signals
P18
S_AXI_ARID[C_S_AXI_ID_
WIDTH-1:0]⁽¹⁾
AXI4
I
-
Read address ID. This signal is the identification tag for
the read address group of signals.
P19
S_AXI_ARADDR[C_S_AXI_
ADDR_WIDTH -1 :0 ]
AXI4
AXI4-Lite
I
-
Read address. The read address bus gives the initial
address of a read burst transaction.
P20 S_AXI_ARLEN[7:0]⁽¹⁾
AXI4
I
-
Burst length. The burst length gives the exact number of
transfers in a burst.
P21 S_AXI_ARSIZE[2:0]⁽¹⁾
AXI4
I
-
Burst size. This signal indicates the size of each transfer
in the burst.
P22 S_AXI_ARBURST[1:0]⁽¹⁾
Burst type. The burst type, coupled with the size
AXI4
I
- information, details how the address for each transfer
within the burst is calculated.
P23 S_AXI_ARVALID
AXI4
AXI4-Lite
I
Read address valid. This signal indicates, when HIGH,
-
that the read address and control information is valid and
remains stable until the address acknowledgement
signal, ARREDY, is high.
P24 S_AXI_ARREADY
AXI4
O
AXI4-Lite
Read address ready. This signal indicates that the slave
0 is ready to accept an address and associated control
signals.
AXI Read Data Channel Signals
P25
S_AXI_RID[C_S_AXI_ID_
WIDTH-1:0]⁽¹⁾
Read ID tag. This signal is the ID tag of the read data
AXI4
O
0
group of signals. The RID value is generated by the slave
and must match the ARID value of the read transaction to
which it is responding.
P26
S_AXI_RDATA[C_S_AXI_
DATA_WIDTH -1:0]
AXI4
AXI4-Lite
O
0 Read data
P27 S_AXI_RRESP[1:0]
AXI4-Lite O
0
Read response. This signal indicates the status of the
read transfer.
P28 S_AXI_RLAST⁽¹⁾
AXI4
O
0
Read last. This signal indicates the last transfer in a read
burst.
P29 S_AXI_RVALID
AXI4
AXI4-Lite ^O
0
Read valid. This signal indicates that the required read
data is available and the read transfer can complete.
P30 S_AXI_RREADY
AXI4
AXI4-Lite
I
-
Read ready. This signal indicates that the master can
accept the read data and response information.
AXI4-Lite Register Interface⁽²⁾
AXI Write Address Channel Signals⁽²⁾
S_AXI_CTRL_AWADDR[C_S
P31 _AXI_CTRL_ADDR_WIDTH- AXI4-Lite I
1:0]⁽²⁾
-
AXI Write address for register interface. The write
address bus gives the address of the write transaction.
P32 S_AXI_CTRL_AWVALID⁽²⁾
AXI4-Lite I
Write address valid for register interface. This signal
- indicates that valid write address and control information
are available.
P33 S_AXI_CTRL_AWREADY⁽²⁾
AXI4-Lite O
Write address ready for register interface. This signal
0x0 indicates that the slave is ready to accept an address and
associated control signals.
DS712 July 25, 2012
www.xilinx.com
9
Product Specification