DS712 Datasheet, PDF (5/61 Pages) Xilinx, Inc – LogiCORE IP AXI PLBv46 Bridge

LogiCORE IP AXI PLBv46 Bridge (v2.02.a)
Write Response (wr_resp)
Implemented only for AXI4 interface and not read only, that is, parameters C_S_AXI_PROTOCOL=”AXI4” and
C_S_AXI_SUPPORTS_WRITE=1. This module generates the response for the write transfer. This also has FIFO (two
deep) to store the transaction IDs generated from AXI.
Read Address State Machine (rd_addr_sm)
Implemented only for AXI4 interface and not write only, that is, parameters C_S_AXI_PROTOCOL=”AXI4” and
C_S_AXI_SUPPORTS_READ=1. This converts the AXI address to the PLB address for the read transfers. This also
does the necessary conversion of burst length in case of narrow transfers generated from AXI to word transfer on
PLB.
Read Data FIFO (rd_data_fifo)
Implemented only for AXI4 interface and not write only, that is, parameters C_S_AXI_PROTOCOL=”AXI4” and
C_S_AXI_SUPPORTS_READ=1. This 32x32 FIFO is used to store the read data generated from PLB and is read on
S_AXI_RREADY.
Read Data State Machine (rd_data_sm)
Implemented only for AXI4 interface and not write only, that is, parameters C_S_AXI_PROTOCOL=”AXI4” and
C_S_AXI_SUPPORTS_READ=1. This reads the data from rd_data_fifo and sends to AXI along with
S_AXI_RVALID and S_AXI_RLAST. This also generates the read response for AXI.
Burst Logic (burst_logic)
Implemented only for AXI4 interface, that is, parameters C_S_AXI_PROTOCOL = ”AXI4”. This is used to generate
the M_wrBurst and M_rdBurst signals for PLB.
PLB Wr Rd Select (plb_wr_rd_sel)
Implemented only for AXI4 interface and when supports both read and write, that is, parameters
C_S_AXI_PROTOCOL = ”AXI4” and C_S_AXI_SUPPORTS_WRITE=1 and C_S_AXI_SUPPORTS_READ=1. This is
used to generate the final address qualifiers on PLB. Default read is always high priority.
Design Parameters
Table 1 shows the design parameters of the AXI to PLBv46 Bridge.
Inferred Parameters
In addition to the parameters listed in Table 1, there are also parameters that are inferred for each AXI interface in
the EDK tools. Through the design, these EDK-inferred parameters control the behavior of the AXI Interconnect.
For a complete list of the interconnect settings related to the AXI interface, see the DS768, AXI Interconnect IP Data
Sheet.
DS712 July 25, 2012
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