DS712 Datasheet, PDF (58/61 Pages) Xilinx, Inc – LogiCORE IP AXI PLBv46 Bridge

LogiCORE IP AXI PLBv46 Bridge (v2.02.a)
Table 15: FPGA Resource Utilization Benchmarks on the Spartan-6 FPGA (xc6slx100tfgg900-3)
Parameter Value
Device Resources
Frequency
NA NA 32 AXI4LITE 1
1
NA NA 32
33
147
86
150
NA 0
32
AXI4
0
1
1
1
32
105
249
319
100
0
0
32
AXI4
1
0
1
1
32
126
479
400
100
0
0
32
AXI4
1
1
1
1
32
230
508
621
100
0
1
32
AXI4
1
1
1
1
32
238
588
774
100
0
1
32
AXI4
1
1
2
2
32
251
755
938
100
1
1
32
AXI4
1
1
1
1
32
400
1133
1340
100
1
1
32
AXI4
1
1
2
2
32
400
1133
1340
100
1
1
64
AXI4
1
1
2
2
32
382
812
938
100
1
1
64
AXI4
1
1
2
2
64
451
955
1184
100
Read Latency and AXI Bandwidth Utilization
The core is configured for the best possible configuration for calculation of latency and bandwidth utilization.
The read latency from address valid (ARVALID) to first data beat (RVALID) (assuming PLB slave latency as one
clock) of AXI to PLBv46 Bridge is shown in Table 16. For the latency calculation, it is assumed that PLB slave
latency (M_request to PLB_MRdDack) is one clock. Latency numbers includes bridge latency and PLB slave
latency.
Table 16: Read latency in AXI clocks
C_S_AXI_PROTOCOL
AXI4LITE
AXI4
Read Latency
2 clocks
3 clocks
DS712 July 25, 2012
www.xilinx.com
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Product Specification