DS712 Datasheet, PDF (24/61 Pages) Xilinx, Inc – LogiCORE IP AXI PLBv46 Bridge

LogiCORE IP AXI PLBv46 Bridge (v2.02.a)
The BESR is shown in Figure 5 and detailed in Table 7. The BEAR is shown in Figure 6 and detailed in Table 8.
X-Ref Target - Figure 5
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Figure 5: Bridge Error Status Register
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Table 7: Bridge Error Status Register (BESR) Description ⁽¹⁾
Bit(s)
Name
Core
Access
Reset
Value
Description
31-16⁽²⁾
MID
R/W
“00”
AXI Write Transaction ID
This value reflects the S_AXI_AWID qualifier at the time of error capture.
15-14 BTYPE
R/W
AXI Write Burst Type
“00”
This value reflects the S_AXI_AWBURST qualifier at the time of error
capture.
13-11 BSIZE
R/W
“000”
AXI Write Burst Size
This value reflects the S_AXI_AWSIZE qualifier at the time of error capture.
10-3
BLEN
R/W
“00000000”
AXI Write Burst Length
This value reflect the S_AXI_AWLEN qualifier at the time of error capture.
2
Reserved R/W
‘0’
Reserved
1
DECERR R/W
Decode Error
This bit is asserted when PLB_MTimeOut is asserted by the PLB. This
‘0’
indicates that there is no slave at the transaction address.
‘0’ = No Decode Error asserted.
‘1’ = Decode Error asserted.
0
SLVERR
R/W
Slave Error
This bit is asserted when PLB_MWrErr is asserted by the PLB. This
‘0’
indicates that the access has reached the PLB slave successfully, but the
slave wishes to return an error condition.
‘0’ = No Slave Error asserted.
‘1’ = Slave Error asserted.
Notes:
1. This register is cleared after reading.
2. Vector length of MID is defined by parameter C_S_AXI_ID_WIDTH
X-Ref Target - Figure 6

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Figure 6: Bridge Error Address Register

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DS712 July 25, 2012
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Product Specification