DS712 Datasheet, PDF (12/61 Pages) Xilinx, Inc – LogiCORE IP AXI PLBv46 Bridge

LogiCORE IP AXI PLBv46 Bridge (v2.02.a)
Table 2: I/O Signal Description (Cont’d)
Port
Signal Name
Interface
I/O
Initial
State
Description
P57
M_ABus[0:(C_MPLB_
AWIDTH - 1)]
PLB
O
0 Master address bus
P58 M_wrBurst
PLB
O
0 Master burst write transfer indicator
P59 M_rdBurst
PLB
O
0 Master read write transfer indicator
P60
M_WrDBus[0:(C_
MPLB_DWIDTH - 1)]
PLB
O
0 Master write data bus
P61 PLB_MaddrAck
PLB
I
- PLB master address acknowledge
P62 PLB_MSSize[0:1]
PLB
I
- PLB slave data bus size
P63 PLB_MTimeout
PLB
I
- PLB master bus time out
P64 PLB_MRdErr
PLB
- PLB master slave read error indicator
P65 PLB_MWrErr
PLB
I
- PLB master slave write error indicator
P66
PLB_MRdDBus[0:(C_MPLB_
DWIDTH - 1)]
PLB
I
- PLB master read data bus
P67 PLB_MRdDAck
PLB
I
- PLB master read data acknowledge
P68 PLB_RdBTerm
PLB
I
- PLB master terminate read burst indicator
P69 PLB_MWrDAck
PLB
I
- PLB master write data acknowledge
PLB Master Unused Output Signals - driven default
P70 M_TAttribute[0:15]⁽³⁾
PLB
O
0
Unused
PLB master transfer attributes
P71 M_lockErr⁽³⁾
Unused
PLB
O
0 _{PLB master lock error}
P73 M_abort⁽³⁾
PLB
O
0
Unused
PLB master abort
P73
M_UABus[0:(C_MPLB_
AWIDTH - 1)]⁽³⁾
PLB
O
0 ^Unused
PLB master upper bits of address bus
P74 MD_Error⁽³⁾
PLB
O
0
Master error detection indicator
Unsupported feature; port driven to logic Low⁽²⁾
P75 M_priority[0:1]⁽³⁾
P76 M_buslock⁽³⁾
Bus request priority
Driven to logic low ²⁾
M_priority is assigned the binary conversion of
C_PLB_MPRIORITY
PLB
O
0 _{“11“ - Highest priority}
“10“ - Next highest
“01“ - Next highest
“00“ - Lowest
PLB
O
0 Bus lock request
PLB Master Unused Input Signals
P77 PLB_MRdWdAddr[0:3]
PLB
I
- PLB master read word address
P78 PLB_MBusy
PLB
I
-
Unused
PLB master slave busy indicator
P79 PLB_MIRQ
PLB
I
- Unused
DS712 July 25, 2012
www.xilinx.com
12
Product Specification