DS712 Datasheet, PDF (22/61 Pages) Xilinx, Inc – LogiCORE IP AXI PLBv46 Bridge

X-Ref Target - Figure 4
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LogiCORE IP AXI PLBv46 Bridge (v2.02.a)
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Figure 4: Byte DataSwap and WrSTRB Swap to BEs as Data Traverses AXI to PLBv46 Bridge
Read and Write Interaction
Consecutive Read and Write transactions or vice versa to the same address issued by AXI, are directly transferred
to PLB, as PLB does not support out of order transactions.
AXI Trustzone and Protection Unit Support
The AXI to PLBv46 Bridge does not support Trustzone. As a consequence, The AR(W)PROT input to the AXI slave
port is ignored and all requests are responded to. If the master port that the AXI to PLBv46 Bridge is connected to
is configured as a secure port and a master attempts a non-secure transaction to the AXI to PLBv46 Bridge, the
interconnect does not present the transaction to the bridge. As a result, the transaction is not presented on the PLB
bus.
AXI signals AR(W)PROT[0] and [2] have no effect on AXI to PLB behavior and the resulting PLB transaction. Bit
0 indicates normal or privileged access, but the PLB does not have any such qualifiers; hence, the response is the
same for normal or privileged accesses. Bit 2 indicates data or instruction access, which again, the PLB does not
qualify and the bridge response is the same for both data and instruction accesses.
AXI Atomic Accesses
The AXI to PLBv46 Bridge does not support AXI atomic exclusive accesses.
PLBv46 Error Conditions - Read and Non-bufferable Write transactions
The bridge executes posted writes and both write and read addresses are pipelined/buffered in the bridge. The
write response (for a non-bufferable transaction) to the AXI is generated after all the data is received by PLB or a
timeout is generated by PLB. The read response is sent along with the data as per AXI protocol.
• Slave Error – PLB_Wr_Err/PLB_Rd_Err from PLB causes the ERROR response to AXI.
• Decode Error – Address phase timeout (assertion of PLB_MTimeout) causes DECERR response to AXI. During
read along with the response, S_AXI_RVALID and S_AXI_RLAST are asserted as per AXI protocol.
DS712 July 25, 2012
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Product Specification