DS712 Datasheet, PDF (16/61 Pages) Xilinx, Inc – LogiCORE IP AXI PLBv46 Bridge

LogiCORE IP AXI PLBv46 Bridge (v2.02.a)
Table 4: AXI to PLB Transaction Translation (Cont’d)
AXI Transaction
PLB Transaction
Note
INCR Write: burst 2 half
word transfers
The possible PLB transfers:
1. Single, Single
2. Single
This is converted to word transfer by aggregating the half words.
On PLB, one single transfer is performed if S_AXI_AWADDR(1)=’0’
else two singles.
If all the valid write strobes are not asserted on the first and/or last
word, a PLB single write is performed on the first and/or last word.
The byte address bits of the first word single PLB transaction are
set based on the first byte enable that is asserted, as required by
PLB protocol.
Address incrementing is performed as necessary to the single
transactions:
From Single to second single address is incremented by 0x04 and
aligned to word boundary.
INCR Write: burst 3 half
word transfers
This breaks into two singles
on PLB
This is converted to word transfer by aggregating the half words.
The byte address bits of the first word single PLB transaction are
set based on the first byte enable that is asserted, as required by
PLB protocol.
Address incrementing is performed as necessary to the single and
burst transaction:
From Single to second single address is incremented by 0x04 and
aligned to word boundary.
INCR Write: burst 4-16
half word transfers
The max burst length of this
is 9 as half words are
converted into words.
This can break into write
transaction (max3) as
follows:
1. Single, Single
2. Single, Single, Single
3. Single, Burst, Single
4. Single, Burst
5. Burst, Single
6. Burst
This is converted to word transfer by aggregating the half words.
If all valid write strobes are not asserted on the first and/or last
word, a PLB single write is performed on the first and/or last word.
The byte address bits of the first word single PLB transaction are
set based on the first byte enable that is asserted, as required by
PLB protocol.
Address incrementing is performed as necessary to the single and
burst transaction:
1. From Single to next transfer, (single or burst) address is
incremented by 0x04 and aligned to word boundary.
2. From Burst to next transfer, (single) address is incremented by
length of transfer during burst, that is, (M_BE + ‘1’).
INCR Read: burst 2-16
Half Word transfers
Burst read 2-9 word
This is converted to word transfer and S_AXI_RDATA has the same
value for two S_AXI_RREADY cycles.
The max burst length of this is 9 as half words are converted into
words.
INCR Write: burst 2-4 byte
transfers
The possible PLB transfers:
1. Single, Single
2. Single
This is converted to word transfer by aggregating the bytes.
On PLB, one single transfer is performed if all the bytes fall in the
same word else two singles.
The byte address bits of the first word single PLB transaction are
set based on the first byte enable that is asserted, as required by
PLB protocol.
From Single to second, single address is incremented by 0x04 and
aligned to word boundary.
DS712 July 25, 2012
www.xilinx.com
16
Product Specification