DS712 Datasheet, PDF (59/61 Pages) Xilinx, Inc – LogiCORE IP AXI PLBv46 Bridge

LogiCORE IP AXI PLBv46 Bridge (v2.02.a)
Best case AXI bandwidth utilization is calculated on AXI by issuing back-to-back burst read and write transfers of
length 255 and observed in simulation by requesting 1000 transfers. See Table 17. For improving core performance,
C_S_AXI_WRITE_ACCEPTANCE and C_S_AXI_READ_ACCEPTANCE need to be set to 2.
Table 17: AXI Bandwidth Utilization
Transfer Type
Utilization in %
Back to back writes
94%
Back to back reads
84%
Back to back reads and writes
83%
Not Supported Features/Limitations
The bridge does not decode address range for PLB Slave.
AXI Master Interface
• AXI data bus width greater than 64 bits
• AXI address bus width is fixed to 32 bits
• AXI Exclusive Accesses
• AXI Trustzone is not supported
• AXI Protection Unit Support is limited
• AXI Low-Power interface is not supported
• In AXI burst write transactions, deasserted write strobes are supported only in the first and last word of the
burst write
• In AXI WRAP write transactions, all the valid byte line must have WSTBs asserted.
• AXI Barrier transactions
• AXI Debug transactions
• AXI user signals
• AXI QOS
PLBv46 Slave Interface
• PLB data bus greater than 64 bits
• PLB address bus width is fixed to 32 bits
• Aborts
• Fixed Length Bursts transfer requests of 17 to 256 data beats
• Fixed Length Bursts of size byte and half word
• Indeterminate Length Bursts
• Premature Fixed Length Burst terminations
• All Cache line transfers
• Transfer attributes
• Pending request and priority input information
• PLBv46 buslock not supported
DS712 July 25, 2012
www.xilinx.com
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Product Specification