DS712 Datasheet, PDF (6/61 Pages) Xilinx, Inc – LogiCORE IP AXI PLBv46 Bridge

LogiCORE IP AXI PLBv46 Bridge (v2.02.a)
Table 1: Design Parameters
Generic
Feature/Description
Parameter Name
Allowable
Values
Default
Values
VHDL
Type
System Parameters
G1 Target FPGA family
C_FAMILY
artix7, virtex7,
kintex7, virtex6,
spartan6
virtex6
string
Bridge Interface Parameters
G2 Enable byte swap for AXI4
G3 Implement Debug register
C_EN_BYTE_SWAP
C_EN_DEBUG_REG ⁽¹⁾
0,1
0
integer
0,1
0
integer
G4
AXI Protocol to connected
master
C_S_AXI_PROTOCOL
“AXI4LITE”,
“AXI4”
“AXI4LITE”
string
G5
Implement Narrow transfer
support
C_S_AXI_SUPPORTS_
NARROW_BURST ⁽¹⁾
0,1
1
integer
G6
Implement Exclusive access
support
C_S_AXI_SUPPORTS_EXCL_
ACCESS ⁽¹⁾
G7 AXI Identification tag width
C_S_AXI_ID_WIDTH ⁽¹⁾
0
1-16
0
integer
4
integer
G8
AXI most significant address
bus width
C_S_AXI_ADDR_WIDTH
32
32
integer
G9 AXI data bus width
C_S_AXI_DATA_WIDTH
32, 64
32
integer
Indicates whether write
G10 channel is included in the
C_S_AXI_SUPPORTS_WRITE ⁽¹⁾
0, 1
design
1
integer
G11
Indicates whether read channel
is included in the design
C_S_AXI_SUPPORTS_READ ⁽¹⁾
0, 1
1
integer
Maximum number of active
G12 write transactions that slave C_S_AXI_WRITE_ACCEPTANCE⁽¹⁾
1, 2
can accept
1
integer
Maximum number of active
G13 read transactions that slave C_S_AXI_READ_ACCEPTANCE⁽¹⁾
1, 2
can accept
1
integer
G14
Indicates if slave supports
barrier transactions
C_S_AXI_SUPPORTS_BARRIERS⁽¹⁾
0
0
integer
G15 Bridge Base Address
C_S_AXI_RINGx_BASEADDR⁽²⁾
Valid Address
All ONEs
std_logic_
vector
G16 Bridge High Address
C_S_AXI_RINGx_HIGHADDR⁽²⁾
Valid Address
All ZEROs
std_logic_
vector
G16 Defines bridge address ranges C_S_AXI_NUM_ADDR_RANGES
1-4
Bridge Register Interface Parameters ⁽³⁾
1
integer
G17
AXI most significant address
bus width
C_S_AXI_CTRL_ADDR_WIDTH⁽³⁾
32
G18 AXI data bus width
C_S_AXI_CTRL_DATA_WIDTH⁽³⁾
32
32
integer
32
integer
G19
Bridge register interface base
address
C_S_AXI_CTRL_BASEADDR⁽²⁾⁽³⁾
Valid Address
All ONEs
std_logic_
vector
G20
Bridge register interface high
address
C_S_AXI_CTRL_HIGHADDR⁽²⁾⁽³⁾
Valid Address
All ZEROs
std_logic_
vector
DS712 July 25, 2012
www.xilinx.com
6
Product Specification