DS712 Datasheet, PDF (13/61 Pages) Xilinx, Inc – LogiCORE IP AXI PLBv46 Bridge

LogiCORE IP AXI PLBv46 Bridge (v2.02.a)
Table 2: I/O Signal Description (Cont’d)
Port
Signal Name
Interface
I/O
Initial
State
Description
P80 PLB_Mrearbitrate
PLB
I
- PLB master bus rearbitrate indicator
P81 PLB_MWrBTerm
PLB
I
- PLB master terminate write burst indicator
Notes:
1. Valid only when C_S_AXI_PROTOCOL=”AXI4”
2. Valid only when C_S_AXI_PROTOCOL=”AXI4” AND C_S_AXI_SUPPORTS_WRITE=1 and C_EN_DEBUG_REG=1
3. Unused port. Output has default assignment.
Allowable Parameter Combinations
The current implementation of the PLBv46 Master Burst has the following restrictions that apply to parameter
value settings. The assigned value for C_MPLB_NATIVE_DWIDTH should be same as C_S_AXI_DATA_WIDTH.
Parameter - I/O Signal Dependencies
The dependencies between the AXI to PLBv46 Bridge core design parameters and I/O signals are described in
Table 3.
Table 3: Parameter - I/O Signal Dependencies
Generic
or Port
Name
Affects Depends
Relationship Description
Design Parameters
G3 C_EN_DEBUG_REG
G17-G20,
P31-P47
G4, G10
• C_EN_DEBUG_REG is invalid when
C_S_AXI_PROTOCOL=”AXI4LITE” or
C_S_AXI_SUPPORTS_WRITE=0.
• G17-G20 & P31-P47- invalid when
C_EN_DEBUG_REG=0
G4 ^{C_S_AXI_PROTOCOL}
G3, G5-G7,
G10-G14,
P1, P3-P6,
P11, P14,
P18, P20,
P25, P28,
P58, P59
• All are invalid if
C_S_AXI_PROTOCOL=”AXI4LITE”
• Input ports are unused output ports are driven to
-
their default.
G5
C_S_AXI_SUPPORTS_
NARROW_BURST
P4, P24
• C_S_AXI_SUPPORTS_NARROW_BURST is
invalid when
G4
C_S_AXI_PROTOCOL=”AXI4LITE”
• P4 & P24 considered having constant value
corresponding to AXI data width when
C_S_AXI_SUPPORTS_NARROW_BURST=0
G6
C_S_AXI_SUPPORTS_
EXCL_ACCESS
-
G4
Invalid when C_S_AXI_PROTOCOL=”AXI4LITE”
G7 C_S_AXI_ID_WIDTH
P3, P14,
P18, P25,
• C_S_AXI_ID_WIDTH is invalid when
G4
C_S_AXI_PROTOCOL=”AXI4LITE”
• Defines the width of the ports
G8 C_S_AXI_ADDR_WIDTH
P2, P19
-
Defines the width of the ports
G9 C_S_AXI_DATA_WIDTH
P9, P10,
P44
-
Defines the width of the ports
DS712 July 25, 2012
www.xilinx.com
13
Product Specification