DS712 Datasheet, PDF (1/61 Pages) Xilinx, Inc – LogiCORE IP AXI PLBv46 Bridge

DS712 July 25, 2012
LogiCORE IP AXI PLBv46 Bridge
(v2.02.a)
Product Specification
Introduction
The Advanced Microcontroller Bus Architecture
(AMBA^®) Advanced eXtensible Interface (AXI4) to
Processor Local Bus (PLB v4.6) Bridge translates AXI
transactions into PLBv46 transactions. It functions as
32/64-bit slave on AXI4 and 32/64-bit master on the
PLB.
Features
The Xilinx AXI to PLBv46 Bridge is a soft Intellectual
Property (IP) core that supports following features:
• AXI4 and PLB v4.6 (Xilinx simplification)
• 1:1 (AXI:PLB) synchronous clock ratio
• 32-bit address on AXI and PLB interfaces
• 32/64-bit data buses on AXI & PLB interfaces (1:1
ratio)
• Write and read data buffering
AXI4 Slave Interface Support
• Configurable AXI4 Interface Categories
• Control (AXI4-Lite) Interface
• Read/Write Interface
• Read-only Interface
• Write-only Interface
• Additional control interface to access internal
registers of the design
• INCR bursts of 1 to 256
• Bursts of 1-16 for FIXED type transfer
• Burst of 2, 4, 8 and 16 for WRAP type transfers
• Configurable support for narrow transfers
• Unaligned transactions
• Early response for bufferable write transfer
LogiCORE IP Facts Table
Core Specifics
Supported
Zynq™-7000⁽²⁾, Virtex®-7, Kintex™-7, Artix™-7,
Device Family⁽¹⁾
Spartan-6⁽³⁾ Virtex-6⁽⁴⁾
Supported User
Interfaces
AXI4, AXI4-Lite, PLBv46
Resources
See Table 11, Table 12,Table 13 Table 14, and
Table 15
Provided with Core
Design Files
ISE®: VHDL
Vivado™: Encrypted RTL
Example Design
Not Provided
Test Bench
Not Provided
Constraints File
Not Provided
Simulation
Model
None
Supported S/W
Driver
N/A
Tested Design Flows⁽⁵⁾
Design Entry
Xilinx Platform Studio (XPS)
Vivado Design Suite⁽⁶⁾
Simulation
Mentor Graphics ModelSim
Synthesis
Xilinx Synthesis Technology (XST)
Vivado Synthesis
Support
Provided by Xilinx@ www.xilinx.com/support
Notes:
1. For a complete list of supported derivative devices, see the
Embedded Edition Derivative Device Support.
2. Supported in ISE Design Suite implementations only.
3. For more information on the Spartan-6 devices, see the
Spartan-6 Family Overview.
4. For more information on the Virtex-6 devices, see the
Virtex-6 Family Overview.
5. For the supported versions of the tools, see the Xilinx
Design Tools: Release Notes Guide.
6. Supports only 7 series devices.
© Copyright 2010–2012 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated brands included herein are
trademarks of Xilinx in the United States and other countries. AMBA and ARM are trademarks of ARM in the EU and other countries. All other trademarks are the
property of their respective owners.
DS712 July 25, 2012
www.xilinx.com
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Product Specification