DS712 Datasheet, PDF (21/61 Pages) Xilinx, Inc – LogiCORE IP AXI PLBv46 Bridge

LogiCORE IP AXI PLBv46 Bridge (v2.02.a)
AXI - INCR/WRAP, Narrow Transfers
AXI supports incremental burst transfer of bytes and half word. These transfers are not supported as per Xilinx PLB
v4.6 simplification. To optimize and obtain better throughput:
• For Writes - All the AXI data is collapsed to convert to a data beat equal to the size of the data bus (wherever
possible) and a burst is initiated on the PLB.
• For Reads - A burst is initiated on the PLB and the S_AXI_RVALID is asserted for more than one cycle,
keeping the same data on S_AXI_RDATA. For example, for the INCR, byte burst from AXI of length four that
starts with address aligned to the word boundary (for example, 0x0, 0x4, 0x8, 0xC), the S_AXI_RDATA will
have the same value for four cycles of S_AXI_RREADY assertion.
Endian Support
The endian conversion is implemented in the design depending on C_EN_BYTE_SWAP.
If C_EN_BYTE_SWAP=0. The possible connection from AXI to PLB for 32-bit data width follows:
• AXI is little endian and PLB is big endian.
• M_ABUS(0 to 31) = S_AXI_AxADDR(31 down to 0)
• M_WrDBUS(0 to 31) = S_AXI_AWDATA(31 down to 0)
• M_BE(0 to 3) = S_AXI_WSTB(3 down to 0)
• S_AXI_AWDATA(31 down to 0) = PLB_MRdDBUS(0 to 31)
• AXI is big endian and PLB is big endian
• M_ABUS(0 to 31) = S_AXI_AxADDR(0 to 31)
• M_WrDBUS(0 to 31) = S_AXI_AWDATA(0 to 31)
• M_BE(0 to 3) = S_AXI_WSTB(0 to 3)
• S_AXI_AWDATA(0 to 31) = PLB_MRdDBUS(0 to 31)
Byte Invariance
Byte invariance is implemented if C_EN_BYTE_SWAP=1.
AXI is little endian and PLB is big endian. The AXI to PLBv46 Bridge maintains byte invariance, or using Xilinx IP
terminology, byte addressing integrity is maintained in the bridge design. This means that 32-bit word data from
any address on the PLBv46 bus has the bytes swapped in traversing the bridge so that the byte data of byte lanes of
the same numerical address offsets yields the same byte data when read by the little endian AXI-side or by a remote
master on the big endian PLB-side. For byte transactions, any byte addressed data read from the AXI side or the PLB
side yields the same byte of data. Write strobe signals from the AXI master port are similarly swapped. Byte and
strobe swapping are shown in Figure 4.
DS712 July 25, 2012
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Product Specification