DS712 Datasheet, PDF (14/61 Pages) Xilinx, Inc – LogiCORE IP AXI PLBv46 Bridge

LogiCORE IP AXI PLBv46 Bridge (v2.02.a)
Table 3: Parameter - I/O Signal Dependencies (Cont’d)
Generic
or Port
Name
Affects Depends
Relationship Description
G10
C_S_AXI_SUPPORTS_
WRITE
P1-P17,
P58
• C_S_AXI_SUPPORTS_WRITE is invalid if
C_S_AXI_PROTOCOL=”AXI4LITE”
G4
• P1-P17, P58 are invalid if
C_S_AXI_SUPPORTS_WRITE=0
• Input ports are unused output ports are driven to
their default.
G11
C_S_AXI_SUPPORTS_
READ
P18-P30,
P59
• C_S_AXI_SUPPORTS_READ is invalid if
C_S_AXI_PROTOCOL=”AXI4LITE”
G4
• P18-P30, P59 are invalid if
C_S_AXI_SUPPORTS_READ=0
• Input ports are unused output ports are driven to
their default.
C_S_AXI_WRITE_
G12 _ACCEPTANCE
-
G8
Invalid if C_S_AXI_PROTOCOL=”AXI4LITE”
G13
C_S_AXI_READ_
ACCEPTANCE
-
G8
Invalid if C_S_AXI_PROTOCOL=”AXI4LITE”
G14
C_S_AXI_SUPPORTS_
BARRIERS
-
G8
Invalid if C_S_AXI_PROTOCOL=”AXI4LITE”
G17
C_S_AXI_CTRL_ADDR_
WIDTH
P31, P41
G2, G8,
G10
• Invalid if C_S_AXI_PROTOCOL=”AXI4LITE” or
C_EN_DEBUG_REG=0 or
C_S_AXI_SUPPORTS_WRITE=0
• Port width depends on the generic
G18
C_S_AXI_CTRL_DATA_WIDTH
P34, P35,
P44
G2, G8,
G10
• Invalid if C_S_AXI_PROTOCOL=”AXI4LITE” or
C_EN_DEBUG_REG=0 or
C_S_AXI_SUPPORTS_WRITE=0
• Port width depends on the generic
G19 C_S_AXI_CTRL_BASEADDR
-
G2, G8,
G10
Invalid if C_S_AXI_PROTOCOL=”AXI4LITE” or
C_EN_DEBUG_REG=0 or
C_S_AXI_SUPPORTS_WRITE=0
G20 C_S_AXI_CTRL_HIGHADDR
-
G2, G8,
G10
Invalid if C_S_AXI_PROTOCOL=”AXI4LITE” or
C_EN_DEBUG_REG=0 or
C_S_AXI_SUPPORTS_WRITE=0
G21 C_MPLB_AWIDTH
P57, P73
-
Port width depends on the generic
G22 C_MPLB_DWIDTH
P53, P60,
P66
-
Port width depends on the generic
G23 C_MPLB_NATIVE_DWIDTH
-
G9
Must be same as C_S_AXI_DATA_WIDTH
DS712 July 25, 2012
www.xilinx.com
14
Product Specification