DS712 Datasheet, PDF (11/61 Pages) Xilinx, Inc – LogiCORE IP AXI PLBv46 Bridge

LogiCORE IP AXI PLBv46 Bridge (v2.02.a)
Table 2: I/O Signal Description (Cont’d)
Port
Signal Name
Interface
I/O
Initial
State
Description
AXI Read Data Channel Signals⁽²⁾
S_AXI_CTRL_RDATA[C_S_
P44 AXI_CTRL_DATA_WIDTH
-1:0]⁽²⁾
AXI4-Lite O
0x0 Read data for register interface
P45 S_AXI_CTRL_RRESP[1:0]⁽²⁾ AXI4-Lite O
Read response for register interface. This signal
indicates the status of the read transfer.
0x0 _{“00“ - OKAY}
“10“ - SLVERR
P46 S_AXI_CTRL_RVALID⁽²⁾
AXI4-Lite O
Read valid for register interface. This signal indicates that
0x0 the required read data is available and the read transfer
can complete.
P47 S_AXI_CTRL_RREADY⁽²⁾
AXI4-Lite I
Read ready for register interface. This signal indicates
- that the master can accept the read data and response
information.
System Ports
P48 MPLB_Clk
System I
- PLB clock to the secondary side of the bridge
P49 MPLB_Rst
System I
- PLB reset
P50 Bridge_Interrupt
System O
0 Error interrupt for bufferable AXI write transactions
PLB Master I/O Signals
P51 M_request
PLB
O
0 Bus request the arbiter
P52 M_RNW
PLB
O
0 PLB read not write
P53
M_BE[0:(C_MPLB_
DWIDTH - 1/8) - 1]
PLB
O
0 Master byte enables
P54 M_Msize[0:1]
Master data bus size
PLB
O
0 ^{“00“ - 32-bit Master (if C_MPLB_NATIVE_DWIDTH=32)}
“01“ - 64 bit Master (if C_MPLB_NATIVE_DWIDTH=64)
P55 M_size[0:3]
Master transfer size
“0000“ - Singles - M_BE determines byte line. Always
“0000“ if C_AXI_TYPE=0
“0001“ - 4 word Cacheline - M_BE ignored
“0010“ - 8 word Cacheline - M_BE ignored
Fixed length burst of data width that do not exceed either
the values of C_MPLB_NATIVE_DWIDTH or
C_MPLB_DWIDTH.
PLB
O
0 _{Burst transfer - length determined by M_BE}
“1000“ - Byte burst - Not supported
“1001“ - Half word burst - Not supported
“1010, - Word burst
“1011“ - Double word burst - Supported if Slave native
data width is 64-bit
“1100“ - Quad word burst - Not supported
“1100“ - Octal word burst - Not supported
P56 M_type[0:2]
PLB
O
0
Master transfer type Driven to logic Low⁽²⁾
“000“ - Memory transfer (only supported)
DS712 July 25, 2012
www.xilinx.com
11
Product Specification