DS712 Datasheet, PDF (23/61 Pages) Xilinx, Inc – LogiCORE IP AXI PLBv46 Bridge

LogiCORE IP AXI PLBv46 Bridge (v2.02.a)
PLBv46 Error Conditions - Bufferable Write Transfer
The bridge executes posted writes and generates an early response (after the assertion of S_AXI_WLAST) to AXI for
the cacheable transactions. There is a possibility of having an error or timeout condition on the PLB for this
transaction. But because the response is sent early now there is no mechanism to inform AXI master about the
failure.
To overcome this situation, registers are implemented in the design that capture the address and other control
information of such errored transaction and generate an interrupt.
More detail about these registers and interrupt is detailed in the following subsections.
Register Descriptions
Table 6 shows all the AXI to PLBv46 Bridge registers and their addresses. All the registers described in the following
sections are implemented only when C_S_AXI_PROTOCOL=”AXI4” AND C_S_AXI_SUPPORTS_WRITE=1 AND
C_EN_DEBUG_REG=1.
Table 6: AXI to PLBv46 Bridge Registers ⁽¹⁾
Base Address + Offset (hex)
Register
Name
C_S_AXI_CTRL_BASEADDR + 0x0 BESR
C_S_AXI_CTRL_BASEADDR + 0x4 BEAR
C_S_AXI_CTRL_BASEADDR + 0x8 DGIE
C_S_AXI_CTRL_BASEADDR + 0xC DIER
Access
Type
R⁽²⁾
R⁽³⁾
R/W
R/W
Default
Value (hex)
Description
0x0
Bridge Error Status Register
0x0
Bridge Error Address Register
0x0
Device Global Interrupt Enable Register
0x0
Device Interrupt Enable Register
Notes:
1. The registers are included only when C_EN_DEBUG_REG is set to 1.
2. This register is cleared after read access to this register.
3. Read only register. Writing into this register has no effect.
Bridge Error Status Register (BESR) and Bridge Error Address Register (BEAR)
The following section details the register descriptions of the BESR and BEAR. These registers are included only
when C_EN_DEBUG_REG = 1.
They are used to provide transaction error information to the user application, typically software. When these
registers are enabled, PLB_Wr_Err or PLB_MTimeout (timeout for write) cause a capture trigger to occur for the
BESR and the BEAR. The BESR captures the AXI transaction qualifiers and the BEAR captures the AXI address for
the first offending command. After captured, the data is retained until the user application reads the data from the
registers. The BSER register gets cleared after reading.
The slave error or decode error can be used to generate an interrupt to the user application. This requires enabling
the Device Global Interrupt Enable Register and Device Interrupt Enable Register. This interrupt can then be used
by the user application to signal the need to service the BESR and BEAR.
When C_EN_DEBUG_REG = 0, the strobe error and errors on the PLB cannot be reported to AXI. It is assumed that
the user application does not issue transactions that generate errors on the PLB.
DS712 July 25, 2012
www.xilinx.com
23
Product Specification